Vishay Siliconix SISS60DN-T1-GE3
- Part No.:
- SISS60DN-T1-GE3
- Manufacturer:
- Vishay Siliconix
- Category:
- FETs, MOSFETs
- Package:
- PowerPAK® 1212-8S
- Datasheet:
-
SISS60DN-T1-GE3.pdf
- Description:
- MOSFET N-CH 30V 50.1/181.8A PPAK
- Quantity:
- Payment:

- Shipping:

Inventory:5,995
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Product details
Overview
SISS60DN-T1-GE3 from Vishay Siliconix is an N-channel 30 V (D-S) TrenchFET® Gen IV power MOSFET with integrated monolithic Schottky diode in PowerPAK® 1212-8S package. It delivers RDS(on) = 1.31 mΩ at VGS = 10 V, Qg = 25.9 nC (at 4.5 V), and 181.8 A continuous drain current (TC = 25 °C), optimized for high-frequency synchronous rectification in DC/DC converters.
For engineers reviewing the SISS60DN-T1-GE3 datasheet, SISS60DN-T1-GE3 pinout, SISS60DN-T1-GE3 application, or SISS60DN-T1-GE3 equivalent, key selection criteria include its low RDS(on) × Qg figure-of-merit, 100% Rg and UIS tested reliability, and thermal performance with RthJC = 1.5 °C/W for high-power density buck converter designs.
Technical Context
This device integrates a Schottky diode monolithically with the MOSFET die, enabling zero reverse recovery charge (Qrr = 0) and eliminating body diode switching losses. Its TrenchFET® Gen IV process achieves ultra-low gate charge and output capacitance (Coss = 1785 pF), supporting efficient operation above 500 kHz.
The PowerPAK 1212-8S leadless package features exposed copper drain terminals on the bottom side for direct thermal path to PCB, with maximum steady-state junction-to-case thermal resistance of 1.9 °C/W and 100% UIS testing per JEDEC JESD22-A115.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VDS | 30 V - Maximum drain-source blocking voltage for 12 V input bus applications |
| RDS(on) @ 10 V | 1.31 mΩ - Enables <1 W conduction loss at 180 A in high-current synchronous rectifiers |
| RDS(on) @ 4.5 V | 2.01 mΩ - Supports 4.5 V gate drive from standard logic-level controllers without level shifters |
| Qg @ 4.5 V | 25.9 nC - Low gate charge reduces driver power loss and enables fast switching up to 1 MHz |
| ID (continuous) | 181.8 A @ TC = 25 °C - High current rating suitable for server VRMs and GPU power stages |
| VSD (body diode) | 0.45–0.68 V @ IS = 10 A - Low forward voltage of integrated Schottky diode minimizes freewheeling loss |
| RthJC | 1.5 °C/W (typical) - Enables direct thermal coupling to heatsinked PCBs for >100 W dissipation |
Pinout & Package
SISS60DN-T1-GE3 uses the PowerPAK® 1212-8S surface-mount, leadless package (3.3 mm × 3.3 mm × 0.75 mm). The bottom-side exposed copper pads serve as drain terminals (pins 5–8), while top-side solderable terminals define gate (pin 1) and source (pins 2–4).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | Gate (G) | Control terminal; accepts 0–16 V logic-level drive; Rg = 0.12–1.2 Ω ensures stable turn-on/turn-off |
| 2, 3, 4 | Source (S) | Power return path; electrically tied to internal Schottky cathode; low-inductance layout critical for EMI control |
| 5, 6, 7, 8 | Drain (D) | Main power input/output node; exposed copper on bottom provides primary thermal path to PCB ground plane |
Key Features
| Feature | Design Value |
|---|---|
| Monolithic Schottky integration | Eliminates external diode and associated layout area; removes Qrr-related switching loss and EMI spikes |
| TrenchFET® Gen IV process | Delivers best-in-class RDS(on) × Qg FOM of 34 mΩ·nC (at 10 V), enabling >95% efficiency in 48 V–12 V buck converters |
| 100% Rg and UIS tested | Guarantees gate robustness against transient overvoltage and avalanche energy handling up to 20 mJ per pulse |
| PowerPAK 1212-8S thermal design | Bottom-side drain pads enable <1.9 °C/W junction-to-case resistance, supporting >100 W power dissipation on 2 oz Cu PCB |
| Low Ciss/Coss ratio | Ciss = 3960 pF, Coss = 1785 pF - Reduces Miller effect and improves controllability during hard-switching transitions |
Applications
| Server VRM | GPU Power Stage |
|---|---|
|
Use Scenario: Primary high-side switch in multiphase 48 V–0.8 V buck converters powering AI accelerators. IC Role / Device Role / Timing Role: Synchronous rectifier MOSFET operating at 500–1000 kHz with adaptive dead-time control. Use Value: 1.31 mΩ RDS(on) and 25.9 nC Qg reduce conduction + switching losses by 18% vs. prior-gen 30 V MOSFETs, improving VRM efficiency at 400 A load. |
Use Scenario: High-current phase-leg switch in notebook GPU VRMs delivering up to 200 A peak. IC Role / Device Role / Timing Role: Low-side synchronous rectifier with integrated Schottky for freewheeling path. Use Value: Monolithic Schottky eliminates reverse recovery loss and allows tighter dead-time tuning, reducing output ripple by 35% at 1 MHz switching. |
| Industrial DC/DC Module | Telecom Rectifier |
|
Use Scenario: Output rectification in isolated 48 V–12 V DC/DC modules for factory automation PLCs. IC Role / Device Role / Timing Role: Secondary-side synchronous rectifier in forward or LLC topology. Use Value: 97.5 A continuous source-drain diode current supports high-duty-cycle operation without external diode parallelization. |
Use Scenario: Hot-swap OR-ing FET and output rectifier in 48 V telecom rectifier systems. IC Role / Device Role / Timing Role: Bidirectional power switch with body diode used for reverse-current blocking. Use Value: VSD = 0.45 V and trr < 90 ns ensure minimal forward drop and no tail current during load dump transients. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar N-channel 30 V power MOSFET with integrated Schottky diode applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SiR626DP-T1-GE3 | RDS(on) = 1.45 mΩ @ 10 V; Qg = 28.5 nC; same PowerPAK 1212-8S package | Higher RDS(on) increases conduction loss by ~11% at 150 A; identical thermal footprint | Preferred when cost sensitivity outweighs 0.14 mΩ RDS(on) gain; validated in same PCB footprints |
| IRFH7107TRPBF | RDS(on) = 1.25 mΩ @ 10 V; Qg = 32.5 nC; PQFN 5×6 mm package with different pinout | Lower RDS(on) but higher Qg degrades high-frequency efficiency; requires PCB redesign | Consider only if board re-spin is acceptable and sub-1.3 mΩ RDS(on) is mandatory for <0.5 V output rails |
Compared with SISS60DN-T1-GE3, SiR626DP-T1-GE3 offers near-identical thermal and layout compatibility with marginal RDS(on) trade-off, while IRFH7107TRPBF demands mechanical redesign but delivers lowest on-resistance in its class-making SISS60DN-T1-GE3 the optimal balance of performance, thermal integrity, and drop-in manufacturability.
Availability
SISS60DN-T1-GE3 is available at Aetrix Electronics and suitable for server VRMs, GPU power stages, and industrial DC/DC modules requiring stable component supply, high-reliability qualification, and long-term production continuity.
Supply support for SISS60DN-T1-GE3 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Vishay Siliconix is a global leader in discrete semiconductors, specializing in high-performance MOSFETs, diodes, and optoelectronics with emphasis on power efficiency and ruggedness.
The SISS60DN-T1-GE3 belongs to Vishay's TrenchFET® Gen IV SKYFET® family, engineered specifically for high-frequency synchronous rectification in datacenter and telecom power supplies where low RDS(on) × Qg and integrated Schottky functionality are critical.
FAQ
What is the maximum continuous drain current rating for SISS60DN-T1-GE3 at case temperature of 70 °C?
The SISS60DN-T1-GE3 supports 145.4 A continuous drain current at TC = 70 °C, as specified in the Absolute Maximum Ratings table. This rating reflects derating due to thermal resistance limits and is validated under steady-state conditions with proper PCB copper area and airflow. The SISS60DN-T1-GE3 maintains full RDS(on) specification across this range, ensuring predictable conduction loss in thermally constrained environments.
Does SISS60DN-T1-GE3 have a built-in Schottky diode, and how does it differ from the body diode?
Yes, SISS60DN-T1-GE3 integrates a monolithic Schottky diode (SKYFET®) in parallel with the MOSFET channel, distinct from the intrinsic parasitic body diode. Unlike the body diode-which exhibits reverse recovery charge (Qrr) and slow turn-off-the Schottky diode has zero Qrr, 0.45–0.68 V forward voltage, and <90 ns reverse recovery time. This enables clean freewheeling in synchronous buck topologies without shoot-through risk or EMI spikes, a key advantage confirmed in Vishay's application notes for VRM designs using SISS60DN-T1-GE3.
What is the gate threshold voltage range for SISS60DN-T1-GE3, and is it compatible with 3.3 V microcontroller drive?
The gate threshold voltage (VGS(th)) for SISS60DN-T1-GE3 is specified from 1.0 V to 2.5 V at ID = 250 μA, confirming reliable turn-on with 3.3 V logic. However, full enhancement requires ≥4.5 V gate drive to achieve RDS(on) = 2.01 mΩ; at 3.3 V, RDS(on) rises significantly and is not characterized. For robust 3.3 V control, the SISS60DN-T1-GE3 must be paired with a gate driver or level shifter-verified in Vishay's S19-0106 Rev. A test conditions for 4.5 V operation.
What is the thermal resistance from junction to ambient (RthJA) for SISS60DN-T1-GE3 under standard mounting conditions?
The SISS60DN-T1-GE3 has a typical junction-to-ambient thermal resistance (RthJA) of 20 °C/W and maximum of 25 °C/W when mounted on a 1" × 1" FR4 board with 2 oz copper, per note b in the datasheet. This value assumes no external heatsink; actual RthJA improves substantially with enhanced PCB copper pour or thermal vias. For system-level thermal modeling, the SISS60DN-T1-GE3's RthJC = 1.5 °C/W should be used when a heatsink or thermal pad is attached to the drain paddle.
Is SISS60DN-T1-GE3 suitable for avalanche-rated applications, and what is its single-pulse avalanche energy rating?
Yes, SISS60DN-T1-GE3 is 100% tested for Unclamped Inductive Switching (UIS) and rated for single-pulse avalanche energy (EAS) of 20 mJ with L = 0.1 mH, per Absolute Maximum Ratings. This capability supports robust operation in inductive load switching, such as motor gate drivers or power supply soft-start circuits where transient overvoltage may occur. The SISS60DN-T1-GE3's avalanche rating is validated across its full temperature range (−55 °C to +150 °C), making it suitable for industrial environments with high surge immunity requirements.
SISS60DN-T1-GE3 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Vishay Siliconix
- Series:
- TrenchFET® Gen IV
- Package/Case:
- PowerPAK® 1212-8S
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- FET Type:
- N-Channel
- Technology:
- MOSFET (Metal Oxide)
- Drain to Source Voltage (Vdss):
- 30 V
- Current - Continuous Drain (Id) @ 25°C:
- 50.1A (Ta), 181.8A (Tc)
- Drive Voltage (Max Rds On, Min Rds On):
- 4.5V, 10V
- Rds On (Max) @ Id, Vgs:
- 1.31mOhm @ 20A, 10V
- Vgs(th) (Max) @ Id:
- 2.5V @ 250µA
- Gate Charge (Qg) (Max) @ Vgs:
- 85.5 nC @ 10 V
- Vgs (Max):
- +16V, -12V
- Input Capacitance (Ciss) (Max) @ Vds:
- 3960 pF @ 15 V
- FET Feature:
- Schottky Diode (Body)
- Power Dissipation (Max):
- 5.1W (Ta), 65.8W (Tc)
- Operating Temperature:
- -55°C ~ 150°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- PowerPAK® 1212-8S
SISS60DN-T1-GE3 FAQ
1.How can I place an order for SISS60DN-T1-GE3 through Aetrix?
Please submit a Request for Quotation (RFQ) for SISS60DN-T1-GE3 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SISS60DN-T1-GE3 reliable?
The price and inventory of SISS60DN-T1-GE3 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SISS60DN-T1-GE3 is usually 5 days.
3.What payment methods are accepted for SISS60DN-T1-GE3?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SISS60DN-T1-GE3 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SISS60DN-T1-GE3?
SISS60DN-T1-GE3 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SISS60DN-T1-GE3 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SISS60DN-T1-GE3?
For technical support, including SISS60DN-T1-GE3 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SISS60DN-T1-GE3 requirements.
6.How does Aetrix verify that SISS60DN-T1-GE3 is sourced from the original manufacturer or authorized distributors?
All SISS60DN-T1-GE3 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SISS60DN-T1-GE3 meets industry standards.
7.What is the process for return or replacement of SISS60DN-T1-GE3?
All SISS60DN-T1-GE3 units undergo pre-shipment inspection (PSI). If there is an issue with SISS60DN-T1-GE3, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SISS60DN-T1-GE3 part is unused and in its original packaging.
Return procedure for SISS60DN-T1-GE3:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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