Vishay Siliconix SIZ918DT-T1-GE3
- Part No.:
- SIZ918DT-T1-GE3
- Manufacturer:
- Vishay Siliconix
- Category:
- FET, MOSFET Arrays
- Package:
- 8-PowerWDFN
- Datasheet:
-
SIZ918DT-T1-GE3.pdf
- Description:
- MOSFET 2N-CH 30V 16A 8POWERPAIR
- Quantity:
- Payment:

- Shipping:

Inventory:20,397
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Product details
Overview
SIZ918DT-T1-GE3 from Vishay Siliconix is a dual N-channel 30 V TrenchFET® Power MOSFET in PowerPAIR® 6 × 5 package, featuring channel-1 RDS(on) = 12.0 mΩ @ VGS = 10 V (16 A), channel-2 RDS(on) = 3.7 mΩ @ VGS = 10 V (28 A), and total gate charge of 6.8 nC (Ch-1) / 32 nC (Ch-2); used in notebook system power and synchronous buck converters.
For engineers reviewing the SIZ918DT-T1-GE3 datasheet, SIZ918DT-T1-GE3 pinout, SIZ918DT-T1-GE3 application, or SIZ918DT-T1-GE3 equivalent, key selection considerations include dual-channel thermal separation, asymmetric current rating (16 A / 28 A), leadless PowerPAIR® thermal performance, and body diode recovery characteristics for high-frequency POL operation.
Technical Context
This device integrates two independent N-channel MOSFETs in a single PowerPAIR® 6 × 5 leadless package with exposed-drain thermal pads: Channel-1 optimized for control FET duty (lower Qg, higher RDS(on)), Channel-2 for synchronous rectification (lower RDS(on), higher Qg). Both channels share common source (S1/D2) and operate at VDS = 30 V max.
It supports 4.5 V and 10 V gate drive, with VGS(th) = 1.0–2.2 V (Ch-1) and 1.2–2.2 V (Ch-2), and exhibits body diode trr = 20–40 ns (Ch-1) / 30–60 ns (Ch-2) under IF = 10 A, dI/dt = 100 A/µs conditions - critical for minimizing shoot-through loss in buck topologies.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VDS | 30 V - maximum drain-source blocking voltage for both channels; defines safe operating range in 12 V and 19 V input notebook POL stages. |
| RDS(on) Ch-1 | 12.0 mΩ @ VGS = 10 V - enables low conduction loss in high-side switching position with moderate current (≤16 A). |
| RDS(on) Ch-2 | 3.7 mΩ @ VGS = 10 V - minimizes conduction loss in low-side synchronous rectifier position handling up to 28 A. |
| Qg Ch-1 / Ch-2 | 6.8 nC / 32 nC - asymmetric gate charge supports optimized drive strength allocation: fast turn-on for control FET, robust drive for high-current sync FET. |
| tr/tf Ch-1 | 12–20 ns / 10–20 ns - fast switching transitions reduce overlap loss in high-frequency (≥500 kHz) buck converters. |
| RthJC Ch-1 / Ch-2 | 3.4 / 1.0 °C/W - low junction-to-case thermal resistance enables direct PCB copper heatsinking via exposed drain pads. |
| VSD | 0.85–1.2 V @ IS = 10 A - forward voltage of integrated body diodes impacts light-load efficiency and dead-time design. |
Pinout & Package
PowerPAIR® 6 × 5 (5 mm × 6 mm) leadless surface-mount package with exposed-drain thermal pads on bottom side; no leads - solder interconnection relies on bottom-side copper area. Pin 1 identifies channel-1 source (S1/D2), with G1, D1, S1/D2, G2, S2 arranged per official outline drawing.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| Pin 1 | Channel-1 Source / Channel-2 Drain (S1/D2) | Common node between both MOSFETs; forms internal half-bridge center tap - requires low-inductance layout for buck converter switching node. |
| Pin 2 | Channel-1 Gate (G1) | Control terminal for high-side FET; driven by dedicated gate driver output with <6.8 nC load. |
| Pin 3 | Channel-1 Drain (D1) | High-side switch output; connects to input rail and inductor - must handle full input voltage and transient spikes. |
| Pin 4 | Channel-2 Gate (G2) | Control terminal for low-side FET; driven with higher-current capability due to 32 nC gate charge. |
| Pin 5 | Channel-2 Source (S2) | Low-side return path; connects to ground plane - requires wide, low-impedance copper pour for 28 A continuous current. |
| Pins 6–8 | Exposed Drain Pads (D1/D2) | Thermal and electrical connection points for both drains; soldered directly to PCB copper for heat dissipation and low RDS(on) stability. |
Key Features
| Feature | Design Value |
|---|---|
| Asymmetric dual-channel integration | Enables optimized high-side/low-side pairing in single-package synchronous buck without external matching. |
| 100 % Rg and UIS tested | Ensures gate resistance consistency and ruggedness against unclamped inductive switching stress in real-world POL transients. |
| PowerPAIR® 6 × 5 leadless construction | Reduces parasitic inductance vs. SO-8, improves thermal coupling to PCB, and eliminates leadframe-related RDS(on) drift. |
| Body diode trr = 20–60 ns | Supports efficient hard-switched operation at ≥500 kHz while limiting reverse recovery loss and EMI generation. |
| Lead (Pb)-free and halogen-free | Meets RoHS 2011/65/EU and JEDEC JS709C requirements for environmentally compliant industrial and computing applications. |
Applications
| Notebook System Power | POL Voltage Regulator |
|---|---|
Use Scenario: Core voltage regulation for Intel Core i-series or AMD Ryzen mobile CPUs requiring dynamic 0.7–1.4 V output at up to 40 A peak. IC Role / Device Role / Timing Role: Dual-channel power switch implementing high-side control FET and low-side synchronous rectifier in single-phase buck converter. Use Value: Asymmetric RDS(on) and Qg minimize total conduction + switching loss across load range, improving battery runtime by >2.5% vs. discrete solutions. | Use Scenario: Point-of-load conversion for FPGA I/O banks or GPU memory interfaces demanding tight regulation and fast transient response. IC Role / Device Role / Timing Role: Integrated half-bridge switch enabling compact, high-density DC/DC modules with minimal external components. Use Value: PowerPAIR® thermal performance sustains 28 A continuous current at TC ≤ 70 °C without heatsink, reducing board area by 35% vs. SO-8 duals. |
| Synchronous Buck Converter | Mobile Graphics Core Supply |
Use Scenario: Main 12 V-to-1 V conversion stage in ultrabook motherboard VRMs operating at 1–2 MHz switching frequency. IC Role / Device Role / Timing Role: Primary power switch pair controlling energy transfer into output inductor; gate timing synchronized to controller PWM signal. Use Value: Low Qgd/Qgs ratio (1.9 nC / 2.6 nC for Ch-1) ensures clean turn-on with minimal Miller-induced delay, supporting stable high-frequency operation. | Use Scenario: Dedicated rail for NVIDIA GeForce RTX mobile GPU shader cores requiring 0.85–1.1 V at up to 35 A with <10 µs transient recovery. IC Role / Device Role / Timing Role: High-efficiency power switch delivering regulated voltage under dynamic GPU workload changes. Use Value: Channel-2's 3.7 mΩ RDS(on) limits I²R loss to <3.6 W at 28 A, enabling thermally constrained thin-profile laptop chassis designs. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual N-channel MOSFET applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SiZ250DT-T1-GE3 | 30 V, 4.5 mΩ / 2.2 mΩ (Ch-1/Ch-2), 10.5 nC / 22 nC - lower RDS(on) but higher Qg asymmetry. | Better suited for higher-current (>30 A) POL where conduction loss dominates; less optimal for 500–800 kHz mid-frequency designs. | Select when prioritizing lowest possible RDS(on) over gate drive simplicity and thermal balance. |
| IRF6642TRPBF | 30 V, 7.0 mΩ / 3.2 mΩ, 13 nC / 24 nC - larger SO-8 footprint, higher RthJA (40 °C/W vs. 24 °C/W). | Compatible with legacy SO-8 layouts but lacks PowerPAIR® thermal performance; requires additional thermal vias and copper area. | Choose only for drop-in replacement in existing SO-8 designs where board rework is prohibited. |
Compared with SiZ250DT-T1-GE3 and IRF6642TRPBF, SIZ918DT-T1-GE3 offers the best balance of low gate charge (6.8 nC Ch-1), moderate RDS(on) (12.0 mΩ), and PowerPAIR® thermal efficiency - making it ideal for space-constrained, mid-power notebook VRMs where drive loss and thermal management are co-critical.
Availability
SIZ918DT-T1-GE3 is available at Aetrix Electronics and suitable for notebook system power, POL voltage regulators, and synchronous buck converters requiring stable component supply, RoHS compliance, and leadless thermal performance.
Supply support for SIZ918DT-T1-GE3 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Vishay Siliconix is a global leader in discrete semiconductors, specializing in power MOSFETs, diodes, and optoelectronics with emphasis on high reliability and thermal performance.
The PowerPAIR® product line delivers dual-MOSFET integration in compact leadless packages for high-efficiency DC/DC conversion in computing, communications, and industrial power systems.
FAQ
What is the maximum continuous drain current rating for each channel of the SIZ918DT-T1-GE3?
The SIZ918DT-T1-GE3 specifies 16 A continuous drain current for Channel-1 and 28 A for Channel-2 at TC = 25 °C. At TC = 70 °C, both channels retain their full rated current (16 A / 28 A), reflecting the PowerPAIR® package's superior thermal capability. Derating applies only under ambient conditions (TA = 25 °C → 14.3 A / 26 A).
Does the SIZ918DT-T1-GE3 require special PCB layout considerations due to its PowerPAIR® package?
Yes - the SIZ918DT-T1-GE3 uses a leadless PowerPAIR® 6 × 5 package with exposed drain pads on the bottom. Layout must include minimum 2.835 mm × 2.12 mm copper pads per drain (per Vishay Doc. 67480), thermal vias under pads, and symmetric trace routing to Pin 1 (S1/D2) to minimize switching node inductance. Manual rework is not recommended.
How does the body diode performance of the SIZ918DT-T1-GE3 impact synchronous buck efficiency?
The SIZ918DT-T1-GE3 body diode exhibits VSD = 0.85–1.2 V and trr = 20–40 ns (Ch-1) / 30–60 ns (Ch-2). These values directly affect light-load efficiency and dead-time optimization: shorter trr reduces reverse recovery loss and EMI, while low VSD minimizes conduction loss during non-overlap intervals - critical for maintaining >92% efficiency at 10% load in notebook VRMs.
Can the SIZ918DT-T1-GE3 be driven directly by standard PWM controllers without external gate drivers?
Yes - the SIZ918DT-T1-GE3's Channel-1 gate charge (6.8 nC) and Channel-2 gate charge (32 nC) are compatible with integrated gate drivers in controllers like ISL958xx or MP249x families. However, for >1 MHz operation or high-current loads (>25 A), a dedicated dual-channel driver (e.g., LM5113) is recommended to ensure clean edge rates and prevent shoot-through.
What is the thermal resistance from junction to case (RthJC) for each channel of the SIZ918DT-T1-GE3?
The SIZ918DT-T1-GE3 has RthJC = 3.4 °C/W (max) for Channel-1 and 1.0 °C/W (max) for Channel-2 under steady-state conditions. This asymmetry reflects the larger die size and optimized thermal path of Channel-2, enabling it to dissipate up to 100 W at TC = 25 °C - a key advantage for high-current synchronous rectification in compact VRMs.
SIZ918DT-T1-GE3 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Vishay Siliconix
- Series:
- TrenchFET®
- Package/Case:
- 8-PowerWDFN
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Technology:
- MOSFET (Metal Oxide)
- Configuration:
- 2 N-Channel (Half Bridge)
- FET Feature:
- Logic Level Gate
- Drain to Source Voltage (Vdss):
- 30V
- Current - Continuous Drain (Id) @ 25°C:
- 16A, 28A
- Rds On (Max) @ Id, Vgs:
- 12mOhm @ 13.8A, 10V
- Vgs(th) (Max) @ Id:
- 2.2V @ 250µA
- Gate Charge (Qg) (Max) @ Vgs:
- 21nC @ 10V
- Input Capacitance (Ciss) (Max) @ Vds:
- 790pF @ 15V
- Power - Max:
- 29W, 100W
- Operating Temperature:
- -55°C ~ 150°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-PowerPair® (6x5)
SIZ918DT-T1-GE3 FAQ
1.How can I place an order for SIZ918DT-T1-GE3 through Aetrix?
Please submit a Request for Quotation (RFQ) for SIZ918DT-T1-GE3 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SIZ918DT-T1-GE3 reliable?
The price and inventory of SIZ918DT-T1-GE3 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SIZ918DT-T1-GE3 is usually 5 days.
3.What payment methods are accepted for SIZ918DT-T1-GE3?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SIZ918DT-T1-GE3 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SIZ918DT-T1-GE3?
SIZ918DT-T1-GE3 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SIZ918DT-T1-GE3 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SIZ918DT-T1-GE3?
For technical support, including SIZ918DT-T1-GE3 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SIZ918DT-T1-GE3 requirements.
6.How does Aetrix verify that SIZ918DT-T1-GE3 is sourced from the original manufacturer or authorized distributors?
All SIZ918DT-T1-GE3 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SIZ918DT-T1-GE3 meets industry standards.
7.What is the process for return or replacement of SIZ918DT-T1-GE3?
All SIZ918DT-T1-GE3 units undergo pre-shipment inspection (PSI). If there is an issue with SIZ918DT-T1-GE3, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SIZ918DT-T1-GE3 part is unused and in its original packaging.
Return procedure for SIZ918DT-T1-GE3:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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