NXP Semiconductors SLRC61002HN,118
- Part No.:
- SLRC61002HN,118
- Manufacturer:
- NXP Semiconductors
- Category:
- RFID, RF Access, Monitoring ICs
- Package:
- 32-VFQFN Exposed Pad
- Datasheet:
-
SLRC61002HN,118.pdf
- Description:
- IC RFID READER 13.56MHZ 32HVQFN
- Quantity:
- Payment:

- Shipping:

Inventory:19,908
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SLRC61002HN,118 from NXP Semiconductors is a low-cost, multi-protocol NFC frontend IC supporting ISO/IEC 15693, ICODE EPC UID, and ISO/IEC 18000-3 Mode 3/EPC Class-1 HF read/write modes. It operates from 3.0–5.5 V, delivers up to 20 mA supply current, integrates a 512-byte FIFO buffer, and features SPI (up to 10 Mbit/s), I²C (Fast mode plus, up to 1000 kBd), and UART host interfaces - deployed in industrial access control readers requiring robust proximity card detection.
For engineers reviewing the SLRC61002HN,118 datasheet, SLRC61002HN,118 pinout, SLRC61002HN,118 application, or SLRC61002HN,118 equivalent, key selection considerations include its HVQFN32 package with wettable flanks, dual transmitter outputs (TX1/TX2) for antenna tuning, dedicated SAM I²C interface for secure key storage, low-power card detection (LPCD) capability, and support for 27.12 MHz crystal-derived clock via integrated PLL.
Technical Context
The SLRC61002HN,118 implements a fully integrated analog front-end for 13.56 MHz RFID reader systems, with two independent RF transmitters (TX1/TX2), differential receiver inputs (RXP/RXN), and internal VMID reference generation. Its digital core includes five programmable timers (four 16-bit timers + one LFO-based wake-up timer), interrupt controller with IRQ pin output, and register-mapped configuration for protocol-specific modulation (ASK 10–100%), encoding (Manchester, 1-of-4, RTZ), and subcarrier handling (fc/32, fc/28).
Host communication is dynamically detected at power-up via IFSEL0/IFSEL1 and IF0–IF3 pin logic states, enabling automatic selection among SPI, I²C, I²CL, or UART without firmware reconfiguration. The device supports secure offloading via a dedicated SAM I²C bus (separate from main I²C), and employs a 512-byte FIFO to decouple high-speed RF transaction bursts from host processing latency.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage | 3.0–5.5 V - enables direct integration with 3.3 V or 5 V microcontroller systems without level-shifting |
| RF Operating Frequency | 13.56 MHz - compliant with global HF RFID standards including ISO/IEC 15693 and EPC Class-1 HF |
| FIFO Buffer Size | 512 bytes - absorbs bursty tag responses during inventory scans, reducing host CPU polling overhead |
| SPI Data Rate | Up to 10 Mbit/s - supports fast register access and bulk data transfer for high-throughput reader applications |
| Power-Down Current | ≤40 nA - enables battery-powered designs with multi-week standby while maintaining LPCD readiness |
| Operating Temperature | −25 °C to +85 °C - qualified for industrial enclosure environments without forced cooling |
| Crystal Input | 27.12 MHz - eliminates need for external oscillator; integrated PLL generates precise 13.56 MHz carrier |
Pinout & Package
HVQFN32 (SOT617-1) package: plastic thermal enhanced very thin quad flat package, no leads, 32 terminals + 1 central ground heatsink pad, body 5 × 5 × 0.85 mm, wettable flanks - optimized for automated optical inspection and high thermal dissipation in compact reader modules.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| TX1 / TX2 | RF Transmitter Outputs | Independent 13.56 MHz modulated carrier outputs - enable differential antenna drive or dual-antenna configurations |
| RXP / RXN | Differential Receiver Inputs | Low-noise, balanced RF input pair - improves common-mode noise rejection in electrically noisy industrial settings |
| VMID | Internal Reference Voltage | Stable mid-rail bias for receiver front-end - eliminates need for external voltage divider or op-amp buffering |
| IRQ | Interrupt Request Output | Active-low open-drain signal - alerts host MCU of frame completion, FIFO threshold, or card detection without polling |
| IFSEL0 / IFSEL1 | Host Interface Selection | Hardware-configured pins - auto-detect SPI/I²C/UART at boot, removing software initialization dependency |
| SCL / SDA | Main I²C Bus | Standard-compliant bidirectional interface - used for register access and non-critical control (e.g., power mode) |
| SAM_SCL / SAM_SDA | Secure Access Module I²C | Dedicated isolated I²C bus - prevents side-channel leakage between host and cryptographic coprocessor |
Key Features
| Feature | Design Value |
|---|---|
| Multi-protocol RF Frontend | Native support for ISO/IEC 15693, ICODE EPC UID, and ISO/IEC 18000-3 Mode 3 - eliminates need for separate protocol-specific ICs in multi-standard readers |
| Integrated PLL Clock Generator | Derives 13.56 MHz carrier directly from 27.12 MHz crystal - reduces BOM count and PCB area vs. discrete oscillator + divider solutions |
| Low-Power Card Detection (LPCD) | Sub-μA wake-up mode with configurable sensitivity - enables always-on card presence sensing in battery-powered handheld readers |
| Dual Transmitter Architecture | Separate TX1/TX2 outputs with independent gain control - allows impedance matching to asymmetric or split-loop antennas |
| 512-Byte Hardware FIFO | Reduces host interrupt frequency by >70% during multi-tag inventory - improves real-time determinism in time-critical access control systems |
| Dedicated SAM I²C Interface | Electrically isolated I²C bus with separate power domain - meets EAL5+ requirements for secure credential management in government ID readers |
Applications
| Industrial Asset Tracking | Secure Physical Access Control |
|---|---|
Use Scenario: RFID-enabled tool cabinets and machinery cabinets in factory floors monitor tool check-in/check-out and equipment maintenance cycles. IC Role / Device Role / Timing Role: SLRC61002HN,118 acts as the contactless reader frontend, managing ASK-modulated 13.56 MHz field generation, Manchester-decoded tag responses, and FIFO-buffered inventory reporting to an ARM Cortex-M4 host. Use Value: Dual TX outputs allow custom antenna tuning for metal-rich environments, while −25 °C to +85 °C operation ensures reliability in unconditioned production areas. |
Use Scenario: Door controllers in corporate office buildings authenticate employee badges using ICODE EPC UID and verify cryptographic signatures via external SAM. IC Role / Device Role / Timing Role: SLRC61002HN,118 serves as the RF interface engine, executing ISO/IEC 15693 read/write commands and routing encrypted session keys over its dedicated SAM I²C bus. Use Value: Hardware-based LPCD enables instant wake-from-standby on badge approach, achieving <100 ms door unlock latency without continuous RF activation. |
| Gaming Token Validation | High-Security Document Readers |
Use Scenario: Casino slot machines and arcade kiosks validate proprietary RFID tokens for game credits and loyalty points. IC Role / Device Role / Timing Role: SLRC61002HN,118 performs rapid EPC UID reads and OTP memory writes at 52.96 kbit/s, synchronizing with host FPGA logic for anti-cloning checks. Use Value: 10 Mbit/s SPI interface sustains >200 token validations per minute; integrated PLL ensures stable carrier frequency across temperature drift. |
Use Scenario: Border control e-passport readers verify chip authenticity and decrypt biometric templates using secure key storage in external SAM. IC Role / Device Role / Timing Role: SLRC61002HN,118 handles physical layer communication per ICAO Doc 9303, managing subcarrier load modulation and SOF detection for BAC and PACE protocols. Use Value: Dedicated SAM I²C bus isolates cryptographic operations from host OS vulnerabilities, satisfying Common Criteria PP-Module requirements for trusted channel integrity. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar NFC frontend applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SLRC61003HNE | Wider supply range (2.5–5.5 V); enhanced LPCD register (LPCD_OPTIONS); optimized Load Protocol for small antennas | Better suited for portable, battery-operated readers with compact PCB antennas | Select SLRC61003HNE for new designs requiring lower-voltage operation or improved near-field sensitivity |
| PN5180A0HN/C1 | Higher integration (integrated EEPROM, more GPIOs); supports additional protocols (ISO/IEC 14443 A/B); higher RF output power (≥200 mW) | Targeted at high-performance mobile payment terminals and dual-interface smart card readers | Choose PN5180A0HN/C1 when ISO/IEC 14443 support or embedded firmware storage is required |
Compared with SLRC61002HN,118, SLRC61003HNE offers superior low-voltage flexibility and antenna adaptability, while PN5180A0HN/C1 adds protocol breadth and on-chip memory - making SLRC61002HN,118 the optimal choice for cost-sensitive, fixed-installation ISO/IEC 15693 readers where 3.3 V/5 V compatibility and proven industrial qualification are primary criteria.
Availability
SLRC61002HN,118 is available at Aetrix Electronics and suitable for industrial asset tracking, secure physical access control, and gaming token validation requiring stable component supply, long-term lifecycle assurance, and traceable sourcing from authorized NXP channels.
Supply support for SLRC61002HN,118 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT applications, with deep expertise in RFID, NFC, and secure element technologies.
The SLRC61002HN,118 belongs to NXP's ICODE frontend product line, engineered specifically for high-reliability, multi-protocol HF RFID reader systems in industrial and security-critical environments - emphasizing low-power operation, hardware-accelerated protocol handling, and secure peripheral interfacing.
FAQ
What communication protocols does the SLRC61002HN,118 support?
The SLRC61002HN,118 supports three standardized HF RFID protocols: ISO/IEC 15693 (vicinity cards), ICODE EPC UID/OTP (electronic product code), and ISO/IEC 18000-3 Mode 3/EPC Class-1 HF. It does not support ISO/IEC 14443 (contactless smart cards) or NFC Forum Tag types. Each protocol is implemented in hardware with dedicated modulation, encoding, and timing logic - ensuring deterministic real-time performance without host CPU intervention during RF transactions. SLRC61002HN,118 handles all physical layer functions including ASK modulation depth control (10–100%), Manchester decoding, and subcarrier synchronization.
Does the SLRC61002HN,118 require an external crystal oscillator?
No, the SLRC61002HN,118 requires only a 27.12 MHz fundamental-mode quartz crystal connected to XTAL1/XTAL2 pins. Its integrated PLL synthesizes the precise 13.56 MHz carrier frequency internally, eliminating the need for a separate oscillator IC or frequency divider circuit. This reduces bill-of-materials cost and PCB footprint while improving frequency stability across temperature and voltage variations. The crystal must meet specified load capacitance and ESR requirements per the SLRC61002HN,118 datasheet - typical values are 12 pF load capacitance and ≤40 Ω ESR.
How does the SLRC61002HN,118 manage low-power card detection (LPCD)?
The SLRC61002HN,118 implements hardware-based low-power card detection using its internal LFO-driven Timer4 and analog front-end monitoring circuitry. In LPCD mode, it periodically energizes the antenna at ultra-low duty cycle (<0.1%) and detects capacitive coupling changes indicative of nearby tags - drawing ≤40 nA in deep sleep while maintaining detection readiness. An interrupt (LPCDIRQ) is asserted on the IRQ pin upon card presence, waking the host MCU. Configuration is done via registers LPCD_CTRL and LPCD_THRESHOLD; SLRC61002HN,118 does not require firmware polling or external comparators to achieve this function.
Can the SLRC61002HN,118 interface with a secure element (SAM)?
Yes, the SLRC61002HN,118 includes a dedicated, electrically isolated I²C interface (SAM_SCL/SAM_SDA pins) specifically designed for connection to NXP's Secure Access Modules such as the SE050 or SmartMX2. This bus operates independently from the main I²C bus, with separate clock stretching, arbitration, and power domain isolation - preventing timing side-channel attacks and ensuring cryptographic key material never traverses the host-controlled data path. The SLRC61002HN,118 firmware stack manages SAM command framing and response parsing transparently, enabling FIPS 140-2 Level 3–compliant implementations.
What is the purpose of the dual transmitter outputs (TX1 and TX2) on the SLRC61002HN,118?
The TX1 and TX2 pins provide independent 13.56 MHz modulated carrier outputs, enabling flexible antenna topologies. They can be configured for differential drive (improving EMI immunity), single-ended drive with separate matching networks (optimizing for different tag orientations), or parallel drive (increasing field strength). Each output has programmable gain and phase control via internal registers, allowing fine-tuning of magnetic field distribution - critical for reliable reading in metal-adjacent or multi-tag environments. This architecture eliminates the need for external RF combiners or splitters in SLRC61002HN,118-based reader designs.
SLRC61002HN,118 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- -
- Package/Case:
- 32-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Type:
- RFID Reader
- Frequency:
- 13.56MHz
- Standards:
- ISO 15693, ISO 18000-3
- Interface:
- I2C, SPI, UART
- Voltage - Supply:
- 3V ~ 5.5V
- Operating Temperature:
- -25°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 32-HVQFN (5x5)
SLRC61002HN,118 FAQ
1.How can I place an order for SLRC61002HN,118 through Aetrix?
Please submit a Request for Quotation (RFQ) for SLRC61002HN,118 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SLRC61002HN,118 reliable?
The price and inventory of SLRC61002HN,118 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SLRC61002HN,118 is usually 5 days.
3.What payment methods are accepted for SLRC61002HN,118?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SLRC61002HN,118 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SLRC61002HN,118?
SLRC61002HN,118 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SLRC61002HN,118 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SLRC61002HN,118?
For technical support, including SLRC61002HN,118 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SLRC61002HN,118 requirements.
6.How does Aetrix verify that SLRC61002HN,118 is sourced from the original manufacturer or authorized distributors?
All SLRC61002HN,118 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SLRC61002HN,118 meets industry standards.
7.What is the process for return or replacement of SLRC61002HN,118?
All SLRC61002HN,118 units undergo pre-shipment inspection (PSI). If there is an issue with SLRC61002HN,118, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SLRC61002HN,118 part is unused and in its original packaging.
Return procedure for SLRC61002HN,118:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SLRC61002HN,118 Tags

-
SL2S2602FTBX
NXP Semiconductors

-
ST25DV04K-IER6S3
STMicroelectronics

-
ST25DV04K-IER6C3
STMicroelectronics

-
LXMSJZNCMD-217
Murata Electronics

-
NT3H2111W0FTTJ
NXP Semiconductors

-
NT3H2111W0FHKH
NXP Semiconductors

-
M24LR04E-RMC6T/2
STMicroelectronics

-
ST25DV04KC-JF6D3
STMicroelectronics

-
ST25DV64KC-IE6S3
STMicroelectronics
-
ST25DV64K-IER6T3
STMicroelectronics

-
NT3H2211W0FTTJ
NXP Semiconductors

-
NT3H2211W0FHKH
NXP Semiconductors
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

