NXP Semiconductors SLRC61002HN,151

Overview

SLRC61002HN,151 from NXP Semiconductors is a low-cost, multi-protocol NFC frontend IC supporting ISO/IEC 15693, ICODE EPC UID, and ISO/IEC 18000-3 Mode 3/EPC Class-1 HF read/write modes. It integrates SPI (up to 10 Mbit/s), I²C (Fast mode plus, up to 1000 kBd), and UART (up to 1228.8 kBd) host interfaces, features a 512-byte FIFO buffer, and operates from 3.0 V to 5.5 V supply. It is used in industrial access control readers requiring secure, low-power card detection.

For engineers reviewing the SLRC61002HN,151 datasheet, SLRC61002HN,151 pinout, SLRC61002HN,151 application, or SLRC61002HN,151 equivalent, key selection considerations include its HVQFN32 package with wettable flanks, support for dedicated SAM interface via separate I²C, low-power card detection (LPCD) capability, and compatibility with 27.12 MHz crystal oscillator for integrated PLL clock generation.

Technical Context

The SLRC61002HN,151 implements a full analog front-end for 13.56 MHz RFID communication, including dual transmitter outputs (TX1/TX2), differential receiver inputs (RXP/RXN), and internal VMID reference. Its digital core includes five programmable timers (four 16-bit timers + one LFO-based wake-up timer), interrupt controller with IRQ pin assertion, and register-banked configuration for RF and protocol parameters.

It supports three distinct contactless protocols with defined modulation schemes (10–30% ASK, 100% ASK), subcarrier options (fc/32, fc/28), and encoding (Manchester, 1-out-of-4, RTZ). Host interface selection is determined at power-up by IFSEL0/IFSEL1 logic levels, enabling automatic detection of SPI, I²C, I²C-L, or UART without firmware reconfiguration.

Key Specifications

Pinout & Package

SLRC61002HN,151 is housed in an HVQFN32 (SOT617-1) package: 5 mm × 5 mm × 0.85 mm, thermal-enhanced, no leads, MSL1, with 32 signal terminals plus central ground heatsink (Pin 33).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar NFC frontend applications.

Compared with SLRC61002HN,151, SLRC61003HNK offers lower minimum supply voltage and refined LPCD tuning for miniaturized readers, while PN5180A0HN/C1 shifts architecture toward embedded NFC controller use cases - neither is pin-compatible, but both serve adjacent HF RFID application segments.

Availability

SLRC61002HN,151 is available at Aetrix Electronics and suitable for industrial asset tracking, secure access control readers, and gaming token validation requiring stable component supply across multi-year production cycles.

Supply support for SLRC61002HN,151 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT applications.

The SLRC610 product line delivers high-performance, cost-optimized NFC frontend ICs designed specifically for industrial-grade ICODE and EPC HF reader systems requiring robust RF performance, low-power operation, and flexible host interfacing.

FAQ

What is the primary function of the SLRC61002HN,151 in an NFC reader system?

The SLRC61002HN,151 serves as the analog and digital frontend IC in HF RFID reader systems, handling RF signal generation (13.56 MHz carrier via TX1/TX2), demodulation (via RXP/RXN), protocol processing (ISO/IEC 15693, EPC UID, ISO/IEC 18000-3 Mode 3), and host communication (SPI/I²C/UART). It does not include an embedded MCU - all higher-layer protocol stack execution resides in the external host processor. The SLRC61002HN,151 enables reliable, standards-compliant tag interrogation while offloading RF complexity from the host.

Does the SLRC61002HN,151 support connection to a Secure Access Module (SAM)?

Yes, the SLRC61002HN,151 includes a dedicated, isolated I²C interface (pins SCL/SDA) specifically for connecting an external Secure Access Module. This interface operates independently from the main host I²C bus, ensuring cryptographic key storage and processing remain physically separated from general-purpose host traffic. The SLRC61002HN,151 supports SAM-based authentication workflows required in high-security access control and payment terminal applications.

What are the power supply requirements for the SLRC61002HN,151?

The SLRC61002HN,151 requires three distinct supply domains: VDD (3.0–5.5 V, digital core), AVDD (3.0–5.5 V, analog section), and TVDD (3.0–5.5 V, transmitter stage). PVDD supplies the power amplifier output stage and must be ≤ VDD. All supplies must be decoupled with appropriate capacitors per the datasheet layout guidelines. The SLRC61002HN,151 draws 17–20 mA typical operating current and only 8 nA in hard power-down mode when PDOWN is asserted.

How does the SLRC61002HN,151 handle host interface selection?

The SLRC61002HN,151 automatically detects its host interface type (SPI, I²C, I²C-L, or UART) during power-up or cold reset by sampling the logic levels on IFSEL0 (Pin 26) and IFSEL1 (Pin 27). These pins are tied to VSS or PAD_VDD to encode the desired interface, and the configuration is latched permanently until the next reset. No firmware configuration or runtime switching is required - the interface is fixed at boot, simplifying hardware design and eliminating software initialization overhead for the SLRC61002HN,151.

What is the role of the IRQ pin on the SLRC61002HN,151?

The IRQ pin (Pin 32) is an active-low, open-drain interrupt output that signals asynchronous events to the host microcontroller. It asserts on conditions including end-of-transmission (TxIRQ), end-of-reception (RxIRQ), low-power card detection (LPCDIRQ), FIFO water-level alerts (HiAlertIRQ/LoAlertIRQ), and timer underflows. The host can configure individual interrupt sources via IRQ0En/IRQ1En registers. Using IRQ eliminates the need for continuous polling of status registers, significantly reducing host CPU load and improving real-time responsiveness in the SLRC61002HN,151-based system.