NXP Semiconductors SLRC61002HN,157

Overview

SLRC61002HN,157 from NXP Semiconductors is a low-cost, multi-protocol NFC frontend IC supporting ISO/IEC 15693, ICODE EPC UID, and ISO/IEC 18000-3 Mode 3/EPC Class-1 HF in read/write mode. It operates from 3.0–5.5 V, integrates a 512-byte FIFO buffer, supports SPI up to 10 Mbit/s, and features dedicated SAM interface for secure key storage and crypto acceleration - deployed in industrial access control readers and gaming authentication terminals.

For engineers reviewing the SLRC61002HN,157 datasheet, SLRC61002HN,157 pinout, SLRC61002HN,157 application, or SLRC61002HN,157 equivalent, this page delivers verified electrical specs, HVQFN32 pin mapping, host interface configuration logic (SPI/I²C/UART), low-power card detection behavior, and real-world design trade-offs versus SLRC61003HN variants.

Technical Context

The SLRC61002HN,157 implements a dual-transmitter analog front-end (TX1/TX2) with RXP/RXN differential receiver inputs, VMID reference generation, and integrated PLL deriving system clock from 27.12 MHz crystal. Its contactless UART handles protocol-specific framing for ISO/IEC 15693 (1.66–26.48 kbit/s reader-to-tag, Manchester subcarrier decoding), EPC UID (RTZ encoding), and EPC Class-1 HF modes.

Host communication is dynamically selected via IFSEL0/IFSEL1 pins, enabling SPI (slave mode, NSS-controlled), I²C (Fast mode up to 400 kBd), or UART (RS232-level compatible, up to 1228.8 kBd). A separate I²C bus connects to external Secure Access Module (SAM), while five programmable timers-including Timer4 as LFO-driven wake-up timer-support LPCD and protocol timing compliance.

Key Specifications

Pinout & Package

SLRC61002HN,157 uses HVQFN32 (SOT617-1): 5 × 5 × 0.85 mm thermal-enhanced quad flat no-lead package with wettable flanks, MSL2 rating, and central ground heatsink (Pin 33).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar NFC frontend applications.

Compared with SLRC61002HN,157, SLRC61003HN,157 offers lower minimum voltage and improved LPCD flexibility but shares identical pinout and protocol support; PN5180A0HN/C1 provides higher integration at the cost of losing dedicated SAM security and multi-protocol configurability.

Availability

SLRC61002HN,157 is available at Aetrix Electronics and suitable for industrial asset tracking, access control readers, and gaming token authentication requiring stable component supply across multi-year production cycles.

Supply support for SLRC61002HN,157 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT markets.

The SLRC610 product line delivers high-performance, low-cost NFC frontend ICs designed specifically for host-controlled RFID reader systems requiring ISO/IEC 15693, EPC UID, and EPC Class-1 HF interoperability with secure SAM integration.

FAQ

What protocols does the SLRC61002HN,157 support?

The SLRC61002HN,157 supports three primary protocols: ISO/IEC 15693 (vicinity), ICODE EPC UID/EPC OTP, and ISO/IEC 18000-3 Mode 3/EPC Class-1 HF - all in read/write mode. It does not support ISO/IEC 14443 or FeliCa. Each protocol uses distinct modulation schemes (ASK, subcarrier load modulation) and data encoding (Manchester, RTZ, 1-out-of-4), all handled by the SLRC61002HN,157's contactless UART without host intervention.

How is host interface selection implemented on the SLRC61002HN,157?

Host interface selection on the SLRC61002HN,157 is determined by strapping IFSEL0 (Pin 26) and IFSEL1 (Pin 27) to VSS or PAD_VDD during power-up reset. This configures Pins IF0–IF3 (28–31) as SPI (MOSI/MISO/SCK/NSS), I²C (SCL/SDA/ADR1/ADR2), I²C-L (low-voltage variant), or UART (RX/TX/n.c./PAD_VDD). The SLRC61002HN,157 auto-detects the interface type - no firmware reconfiguration is needed after initial setup.

Does the SLRC61002HN,157 include an integrated crystal oscillator?

The SLRC61002HN,157 does not include a fully integrated crystal oscillator but integrates a PLL and inverting amplifier circuit that accepts a 27.12 MHz fundamental-mode quartz crystal directly on XTAL1 (Pin 19) and XTAL2 (Pin 20). This eliminates the need for an external oscillator module while maintaining precise RF carrier frequency stability - a key requirement for ISO/IEC 15693 compliance. The SLRC61002HN,157 derives all internal clocks from this source.

What is the purpose of the separate SAM interface on the SLRC61002HN,157?

The dedicated I²C interface (SCL/SDA pins reserved exclusively for SAM) on the SLRC61002HN,157 isolates cryptographic operations from the main host bus. It enables secure key storage, AES-128 encryption/decryption, and mutual authentication offload - critical for payment-grade or government ID applications. This architecture prevents side-channel attacks and ensures that sensitive keys never traverse the primary host interface, preserving the security model defined in the SLRC61002HN,157 specification.

How does low-power card detection (LPCD) work on the SLRC61002HN,157?

LPCD on the SLRC61002HN,157 uses Timer4 driven by the internal low-frequency oscillator (LFO) to periodically activate the RF front-end for brief card presence checks. When no card is detected, the device returns to hard power-down (8 nA typical). Detection triggers LPCDIRQ interrupt and wakes the host. Unlike continuous polling, this method achieves microamp-level average current - validated for battery-operated SLRC61002HN,157 deployments requiring weeks of standby life.