NXP Semiconductors SLRC61002HN,551

Overview

SLRC61002HN,551 from NXP Semiconductors is a low-cost, multi-protocol NFC frontend IC supporting ISO/IEC 15693, ICODE EPC UID, and ISO/IEC 18000-3 Mode 3/EPC Class-1 HF read/write modes. It integrates SPI (up to 10 Mbit/s), I²C (Fast mode up to 400 kBd), and UART interfaces, features a 512-byte FIFO buffer, and operates from 3.0–5.5 V supply. It is used in industrial access control readers requiring secure, low-power card detection.

For engineers reviewing the SLRC61002HN,551 datasheet, SLRC61002HN,551 pinout, SLRC61002HN,551 application, or SLRC61002HN,551 equivalent, key selection considerations include its HVQFN32 package with wettable flanks, support for dedicated SAM interface, low-power card detection (LPCD) capability, and compatibility with 27.12 MHz crystal-based clock generation.

Technical Context

The SLRC61002HN,551 implements a full analog front-end for 13.56 MHz RFID communication, including dual TX outputs (TX1/TX2), differential RX inputs (RXP/RXN), and internal VMID reference. Its digital core includes five timers (four programmable + one LFO-based wake-up timer), interrupt controller with IRQ pin, and register-mapped configuration for protocol-specific modulation schemes (ASK, Manchester, RTZ).

It supports host interface auto-detection via IFSEL0/IFSEL1 pins and provides separate I²C for Secure Access Module (SAM) integration. The integrated PLL derives system clocks from a 27.12 MHz quartz, eliminating external clock sources while maintaining timing accuracy for ISO/IEC 15693 subcarrier frequencies (fc/32, fc/28) and EPC UID framing.

Key Specifications

Pinout & Package

HVQFN32 (SOT617-1) package with 32 terminals + central ground heatsink pad (Pin 33). Thermal-enhanced construction enables stable operation at full RF output power without external heatsinking.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar NFC frontend applications.

Compared with SLRC61002HN,551, SLRC61003HNE offers improved flexibility for low-power and small-antenna use cases, while PN5180A0HN/C1 trades ISO/IEC 18000-3 support for broader NFC Forum coverage and reduced external component count - neither is pin-compatible, requiring PCB redesign.

Availability

SLRC61002HN,551 is available at Aetrix Electronics and suitable for industrial asset tracking, secure physical access control, and gaming token authentication requiring stable component supply across extended product lifecycles.

Supply support for SLRC61002HN,551 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT markets, with deep expertise in RFID and NFC technology.

The SLRC610 series is designed specifically for high-reliability, multi-protocol HF RFID reader applications - balancing cost-efficiency, low-power operation, and seamless integration with secure modules and industrial host processors.

FAQ

What protocols does the SLRC61002HN,551 support?

The SLRC61002HN,551 supports three standardized HF RFID protocols: ISO/IEC 15693 (vicinity cards), ICODE EPC UID/OTP (EPCglobal HF), and ISO/IEC 18000-3 Mode 3 (EPC Class-1 HF). It handles all physical layer functions - ASK modulation, Manchester/RTZ decoding, subcarrier generation (fc/32, fc/28), and frame synchronization - without host intervention. Each protocol is selectable via register configuration, and the SLRC61002HN,551 maintains independent timing parameters for each mode.

Does SLRC61002HN,551 require an external crystal?

Yes, the SLRC61002HN,551 requires a 27.12 MHz fundamental-mode quartz crystal connected between XTAL1 and XTAL2 pins. This crystal feeds the on-chip PLL, which generates all internal clocks including the 13.56 MHz RF carrier and digital system clocks. No external oscillator is needed - the SLRC61002HN,551's integrated PLL eliminates clock source components, reducing bill-of-materials and board space versus discrete oscillator solutions.

How does the SLRC61002HN,551 handle low-power card detection (LPCD)?

The SLRC61002HN,551 implements hardware-accelerated LPCD using its internal LFO-driven Timer4 and dedicated analog front-end sampling circuitry. In LPCD mode, it draws only ~8 nA while periodically energizing the antenna and detecting near-field coupling changes. Detection events trigger the IRQ pin and can wake the host from sleep. Configuration registers (e.g., LPCD_OPTIONS in SLRC61003 variants) allow tuning sensitivity and timeout - though SLRC61002HN,551 uses the base LPCD implementation defined in Rev. 5.1 of the datasheet.

Can SLRC61002HN,551 interface directly with a Secure Access Module (SAM)?

Yes, the SLRC61002HN,551 includes a dedicated, isolated I²C interface (separate from the main SCL/SDA pins) specifically for connecting an external Secure Access Module. This SAM interface operates independently, allowing cryptographic operations (e.g., AES-128, DES) and secure key storage to occur off-host while maintaining tamper-resistant separation. The SLRC61002HN,551 forwards encrypted command streams to the SAM and relays decrypted responses - essential for PCI PTS or Common Criteria compliant access systems.

What is the maximum data rate supported by SLRC61002HN,551 in ISO/IEC 15693 mode?

In ISO/IEC 15693 reader-to-tag direction, the SLRC61002HN,551 supports up to 26.48 kbit/s using 10–30% ASK modulation and 1/4 bit encoding. In tag-to-reader direction, it supports up to 52.96 kbit/s using single-subcarrier load modulation at fc/32 with Manchester coding. These rates are achievable under optimal antenna coupling and comply fully with ISO/IEC 15693-2:2018 timing tolerances - verified in NXP's characterization reports for SLRC61002HN,551 at 25 °C and 3.3 V supply.