NXP Semiconductors SLRC61002HN,557
- Part No.:
- SLRC61002HN,557
- Manufacturer:
- NXP Semiconductors
- Category:
- RFID, RF Access, Monitoring ICs
- Package:
- 32-VFQFN Exposed Pad
- Datasheet:
-
SLRC61002HN,557.pdf
- Description:
- IC RFID READER 13.56MHZ 32HVQFN
- Quantity:
- Payment:

- Shipping:

Inventory:4,822
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Product details
Overview
SLRC61002HN,557 from NXP Semiconductors is a low-cost, multi-protocol NFC frontend IC supporting ISO/IEC 15693, ICODE EPC UID, and ISO/IEC 18000-3 Mode 3/EPC Class-1 HF read/write modes. It operates from 3.0–5.5 V, integrates a 512-byte FIFO buffer, and delivers up to 10 Mbit/s SPI, 400–1000 kBd I²C, and 1228.8 kBd UART host interfaces - enabling high-throughput RFID reader designs for industrial access control systems.
For engineers reviewing the SLRC61002HN,557 datasheet, SLRC61002HN,557 pinout, SLRC61002HN,557 application, or SLRC61002HN,557 equivalent, this page provides verified technical context, validated pin functions, real-world use cases, and confirmed alternative options - all grounded in NXP's Rev. 5.1 (Jan 2024) product data sheet and ordering documentation.
Technical Context
The SLRC61002HN,557 implements a dual-transmitter analog front-end (TX1/TX2) with RXP/RXN differential receiver inputs, VMID reference generation, and integrated PLL deriving system clock from a 27.12 MHz crystal. Its contactless UART handles protocol-specific framing for three distinct RFID standards without host intervention.
It features a dedicated SAM interface (separate I²C bus), five programmable timers (including Timer4 for low-power wake-up), and interrupt-driven operation via IRQ pin with 16 configurable sources - including TxIRQ, RxIRQ, LPCDIRQ, and FIFO water-level alerts - enabling efficient host firmware control of RF transactions and power states.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage | 3.0–5.5 V - supports direct integration with 3.3 V or 5 V microcontroller systems without level-shifting. |
| RF Protocol Support | ISO/IEC 15693, ICODE EPC UID, ISO/IEC 18000-3 Mode 3 - enables interoperability with ICODE SLI/SXL tags and EPCglobal HF Class-1 devices. |
| FIFO Buffer Size | 512 bytes - eliminates host polling overhead and sustains burst-mode tag reads/writes at full interface speed. |
| SPI Speed | Up to 10 Mbit/s - allows sub-millisecond register access and rapid command-response cycles in high-throughput readers. |
| Power-Down Current | 8 nA typical - enables battery-powered access terminals to maintain card-detection readiness for months on coin cells. |
| Operating Temperature | −25 °C to +85 °C - qualified for industrial enclosures and outdoor access panels without thermal derating. |
| Host Interfaces | SPI, I²C (Fast/Fast+), UART (RS232-level compatible) - offers flexible MCU connectivity without external bridge ICs. |
Pinout & Package
SLRC61002HN,557 is housed in a HVQFN32 (SOT617-1) package: 5 × 5 × 0.85 mm, thermally enhanced, wettable flanks, MSL2, 32 signal terminals plus central ground heatsink (Pin 33).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (TDO/OUT0) | Boundary scan output / GPIO | Enables JTAG debugging or expands host I/O count without additional logic. |
| 12–13 (RXP, RXN) | Differential RF receiver input | Accepts balanced antenna signals for noise-immune demodulation of ISO15693 subcarrier responses. |
| 15, 17 (TX2, TX1) | Modulated 13.56 MHz transmitter outputs | Drive parallel or series-tuned antennas; support simultaneous dual-antenna configurations. |
| 19–20 (XTAL1, XTAL2) | 27.12 MHz crystal oscillator interface | Eliminates need for external clock generator; integrated PLL ensures precise RF carrier synthesis. |
| 28–31 (IF0–IF3) | Configurable host interface pins | Auto-detect SPI/I²C/UART mode via IFSEL0/IFSEL1 voltage levels - no firmware reconfiguration required. |
| 32 (IRQ) | Interrupt request output | Signals frame completion, card detection, or FIFO threshold events - reduces host polling latency by >90%. |
Key Features
| Feature | Design Value |
|---|---|
| Multi-standard RFID frontend | Single IC replaces discrete analog frontends for ISO15693, EPC UID, and ISO18000-3 Mode 3 - cuts BOM cost and PCB area by 40% vs. legacy solutions. |
| Integrated 512-byte FIFO | Decouples host processing from RF timing constraints - enables deterministic response to fast inventory commands (e.g., 100+ tags/sec). |
| Low-power card detection (LPCD) | Consumes only 8 nA in deep sleep while detecting nearby tags - extends battery life in portable readers beyond 12 months. |
| Dedicated SAM I²C interface | Offloads cryptographic operations (AES, DES) to secure element - meets ISO/IEC 7816-3 and Common Criteria EAL5+ requirements. |
| Five independent timers | Timer4 driven by internal LFO enables autonomous wake-up from standby - eliminates host MCU involvement in periodic card-scan cycles. |
Applications
| Industrial Asset Tracking | Secure Physical Access Control |
|---|---|
|
Use Scenario: RFID readers embedded in factory floor kiosks scan metal-mounted ICODE SLIX tags on tools, pallets, and containers. IC Role / Device Role / Timing Role: SLRC61002HN,557 acts as the analog/digital baseband processor - generating 13.56 MHz carrier, demodulating Manchester-encoded replies, and buffering tag IDs before SPI transfer to ARM Cortex-M4 host. Use Value: Differential RXP/RXN inputs reject EMI from motors and welders; 85 °C rating ensures stable operation inside uncooled enclosures. |
Use Scenario: Wall-mounted door readers authenticate employees using ICODE SLI-S cards during shift changes. IC Role / Device Role / Timing Role: SLRC61002HN,557 executes ISO/IEC 15693 anti-collision, validates UID, and triggers SAM-based AES-128 challenge-response via dedicated I²C bus. Use Value: Hardware-accelerated crypto offload reduces authentication time to <120 ms; IRQ pin enables instant door unlock upon successful verification. |
| Gaming Token Validation | High-Speed Inventory Management |
|
Use Scenario: Slot machines verify authenticity of RFID-enabled gaming chips placed on sensor pads. IC Role / Device Role / Timing Role: SLRC61002HN,557 performs rapid UID read and CRC validation in <35 ms, then asserts IRQ to initiate payout logic. Use Value: 10 Mbit/s SPI interface synchronizes chip ID with game state engine; low-latency LPCD detects chip placement before mechanical actuation. |
Use Scenario: Handheld warehouse scanners perform bulk reads of palletized goods tagged with EPC Class-1 HF labels. IC Role / Device Role / Timing Role: SLRC61002HN,557 manages ISO18000-3 Mode 3 framing, processes 4-pulse 848 kbit/s subcarrier responses, and streams decoded EPCs via FIFO to host. Use Value: 512-byte FIFO absorbs burst traffic from 50+ tags; auto-restart timers enable continuous scanning without host intervention. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar NFC frontend applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SLRC61003HNE | Wider supply range (2.5–5.5 V); enhanced LPCD register (LPCD_OPTIONS); optimized load protocol for small antennas. | Better suited for compact, battery-powered handhelds with miniature loop antennas. | Select SLRC61003HNE for new designs requiring lower-voltage operation or improved near-field sensitivity. |
| PN5180A0HN/C1 | Supports NFC Forum Type A/B/F/ISO14443A/B; higher RF output (1.5 W); integrated NFC controller stack; no SAM interface. | Targets smartphone-like tap-to-pay readers, not industrial ISO15693 infrastructure. | Choose PN5180A0HN/C1 only when NFC Forum compliance or higher RF power is mandatory - not for pure ICODE/EPC HF deployments. |
Compared with SLRC61002HN,557, SLRC61003HNE improves low-voltage flexibility and antenna adaptability, while PN5180A0HN/C1 shifts focus to NFC Forum protocols and embedded software stacks - making SLRC61002HN,557 the optimal choice for cost-sensitive, ISO15693-centric industrial readers requiring hardware crypto offload.
Availability
SLRC61002HN,557 is available at Aetrix Electronics and suitable for industrial asset tracking, secure physical access control, and gaming token validation requiring stable component supply across multi-year production cycles.
Supply support for SLRC61002HN,557 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global leader in secure connectivity solutions, specializing in RFID, NFC, automotive radar, and edge AI processors - with over 20 years of leadership in contactless identification ICs.
The SLRC610 product line delivers high-performance, low-cost NFC frontends optimized for industrial and commercial readers targeting ISO/IEC 15693, EPC UID, and ISO/IEC 18000-3 Mode 3 protocols - emphasizing robust RF performance, minimal external components, and seamless SAM integration.
FAQ
What is the primary function of the SLRC61002HN,557 in an RFID reader system?
The SLRC61002HN,557 serves as the core analog and digital frontend IC in HF RFID readers - handling 13.56 MHz carrier generation, ASK/FSK modulation/demodulation, ISO/IEC 15693/EPC UID/ISO18000-3 protocol framing, and host communication via SPI/I²C/UART. It directly drives the antenna circuit and buffers data for the host microcontroller, eliminating the need for discrete RF components in SLRC61002HN,557-based designs.
Does the SLRC61002HN,557 support secure cryptographic operations?
Yes - the SLRC61002HN,557 includes a dedicated I²C interface for connecting a Secure Access Module (SAM). This allows offloading AES, DES, and other cryptographic functions to a certified secure element, enabling compliant implementations of challenge-response authentication and encrypted tag communication - a capability built into the SLRC61002HN,557 silicon architecture.
What is the significance of the 512-byte FIFO buffer in the SLRC61002HN,557?
The 512-byte FIFO buffer in the SLRC61002HN,557 decouples RF transaction timing from host processor latency - allowing uninterrupted reception/transmission of multi-tag inventory responses or large EPC data blocks. This eliminates byte-by-byte polling and enables burst transfers over SPI at up to 10 Mbit/s, significantly improving throughput in high-density tag environments for the SLRC61002HN,557.
How does the SLRC61002HN,557 achieve ultra-low-power card detection?
The SLRC61002HN,557 achieves 8 nA power-down current via hardware-controlled deep-sleep mode, where only the low-frequency oscillator and LPCD circuitry remain active. It autonomously monitors antenna field perturbations and asserts the IRQ pin upon card presence - enabling battery-powered readers to operate for >12 months on a single CR2032 cell without compromising detection reliability in the SLRC61002HN,557.
Which host interface modes does the SLRC61002HN,557 support, and how are they selected?
The SLRC61002HN,557 supports SPI (up to 10 Mbit/s), I²C (Fast/Fast+), and UART (RS232-level compatible) - selected automatically at power-up by sampling IFSEL0/IFSEL1 pin voltages. Interface configuration is fixed by external pull-up/down resistors on Pins 26–27 and IF0–IF3 (Pins 28–31), requiring no firmware initialization - a key design simplification inherent to the SLRC61002HN,557 architecture.
SLRC61002HN,557 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- -
- Package/Case:
- 32-VFQFN Exposed Pad
- Packaging:
- Tray
- Product Status:
- Obsolete
- Type:
- RFID Reader
- Frequency:
- 13.56MHz
- Standards:
- ISO 15693, ISO 18000-3
- Interface:
- I2C, SPI, UART
- Voltage - Supply:
- 3V ~ 5.5V
- Operating Temperature:
- -25°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 32-HVQFN (5x5)
SLRC61002HN,557 FAQ
1.How can I place an order for SLRC61002HN,557 through Aetrix?
Please submit a Request for Quotation (RFQ) for SLRC61002HN,557 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SLRC61002HN,557 reliable?
The price and inventory of SLRC61002HN,557 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SLRC61002HN,557 is usually 5 days.
3.What payment methods are accepted for SLRC61002HN,557?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SLRC61002HN,557 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SLRC61002HN,557?
SLRC61002HN,557 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SLRC61002HN,557 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SLRC61002HN,557?
For technical support, including SLRC61002HN,557 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SLRC61002HN,557 requirements.
6.How does Aetrix verify that SLRC61002HN,557 is sourced from the original manufacturer or authorized distributors?
All SLRC61002HN,557 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SLRC61002HN,557 meets industry standards.
7.What is the process for return or replacement of SLRC61002HN,557?
All SLRC61002HN,557 units undergo pre-shipment inspection (PSI). If there is an issue with SLRC61002HN,557, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SLRC61002HN,557 part is unused and in its original packaging.
Return procedure for SLRC61002HN,557:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SLRC61002HN,557 Tags

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SL2S2602FTBX
NXP Semiconductors

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ST25DV04K-IER6S3
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STMicroelectronics

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M24LR04E-RMC6T/2
STMicroelectronics

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STMicroelectronics
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ST25DV64K-IER6T3
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