onsemi SMF05CT1
- Part No.:
- SMF05CT1
- Manufacturer:
- onsemi
- Category:
- TVS Diodes
- Package:
- 6-TSSOP, SC-88, SOT-363
- Datasheet:
-
SMF05CT1.pdf
- Description:
- TVS DIODE 5VWM 12.5V SC88/SC70-6
- Quantity:
- Payment:

- Shipping:

Inventory:7,815
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SMF05CT1 from onsemi is a 5-line monolithic transient voltage suppressor (TVS) array in SC-88 package, designed for ESD and surge protection of high-speed data lines. It features 5.0 V reverse working voltage, 9.8 V clamping voltage at 5 A, 100 W peak pulse power, 80–130 pF line-to-GND capacitance, and IEC 61000-4-2 ±15 kV (air)/±8 kV (contact) ESD compliance - deployed in USB, serial port, and automotive infotainment interfaces.
For engineers reviewing the SMF05CT1 datasheet, pinout, applications, or equivalent options, key selection criteria include clamping voltage margin vs. signal swing, junction capacitance impact on signal integrity, SC-88 footprint compatibility with high-density PCB layouts, and Class 3B HBM/Class C MM ESD rating for portable electronics design.
Technical Context
The SMF05CT1 implements a common-anode TVS architecture with five independent cathodes and one shared anode terminal, enabling simultaneous bidirectional overvoltage clamping across five signal lines without cross-talk. Its silicon avalanche structure delivers fast response (<1 ns) to ESD transients and robust 8×20 µs surge handling up to 8.0 A peak pulse current.
Rated for −40°C to +125°C operating junction temperature and UL 94 V-0 flammability, the device supports automotive-grade reliability requirements while maintaining low leakage (<5.0 µA at VRWM = 5 V) and stable clamping performance across temperature and pulse repetition.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Reverse Working Voltage (VRWM) | 5.0 V - Maximum continuous DC or peak AC voltage the protected line can sustain without triggering clamping. |
| Clamping Voltage (VC) | 9.8 V at IPP = 5 A - Voltage level clamped during 8×20 µs surge; ensures downstream ICs (e.g., USB PHY) remain below absolute max ratings. |
| Peak Pulse Power (PPK) | 100 W - Sustains single 8×20 µs transient events per IEC 61000-4-5; defines surge energy absorption capability. |
| Junction Capacitance (CJ) | 80–130 pF @ 0 V, 1 MHz - Impacts high-speed signal rise time and insertion loss; suitable for ≤480 Mbps USB 2.0 but not USB 3.0. |
| ESD Rating | ±15 kV air / ±8 kV contact per IEC 61000-4-2 - Meets industrial and automotive ESD immunity standards for exposed connectors. |
| Operating Temperature | −40°C to +125°C - Supports under-hood automotive and industrial edge computing environments without derating. |
Pinout & Package
SC-88 (Case 419B, Style 24) surface-mount package: 6-pin, 2.0 mm × 1.25 mm × 0.95 mm body, lead pitch 0.65 mm, Pb-free compatible, UL 94 V-0 rated epoxy molding compound.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| Pin 1 | Cathode (Line 1) | Protected signal path #1; connects to I/O line requiring bidirectional ESD clamping to common anode. |
| Pin 2 | Anode (Common) | Shared reference node tied to system ground or chassis; carries aggregate surge current from all five lines. |
| Pin 3 | Cathode (Line 2) | Protected signal path #2; electrically isolated from other cathodes to prevent coupling during multi-line transients. |
| Pin 4 | Cathode (Line 3) | Protected signal path #3; enables compact protection of parallel bus lines (e.g., UART TX/RX/CTS/RTS). |
| Pin 5 | Cathode (Line 4) | Protected signal path #4; supports differential pair or single-ended line protection in space-constrained designs. |
| Pin 6 | Cathode (Line 5) | Protected signal path #5; completes full 5-line coverage for interfaces like SPI or multi-lane sensor buses. |
Key Features
| Feature | Design Value |
|---|---|
| Monolithic 5-line common-anode architecture | Reduces PCB area by 75% vs. discrete TVS diodes; eliminates inter-device timing skew in multi-line ESD events. |
| 100 W peak pulse power (8×20 µs) | Withstands IEC 61000-4-5 Level 3 surges (1 kV line-to-ground) without degradation in automotive CAN/LIN interfaces. |
| IEC 61000-4-2 ±15 kV air / ±8 kV contact | Meets EN 55032/55035 and ISO 10605 requirements for consumer and automotive infotainment touch panels. |
| Low leakage current (<5.0 µA @ 5 V) | Prevents signal distortion or bias shift in high-impedance analog sensor inputs or battery-powered MCU GPIOs. |
| SC-88 footprint with 0.65 mm pitch | Enables routing beneath fine-pitch microcontrollers (e.g., QFN-48) and supports automated optical inspection (AOI) compatibility. |
Applications
| USB 2.0 Interface Protection | Automotive Infotainment Display Port |
|---|---|
|
Use Scenario: Protecting D+ and D− lines, VBUS sense, ID pin, and accessory detect in smartphone docking stations and vehicle-mounted USB hubs. IC Role / Device Role / Timing Role: Bidirectional TVS array clamping ESD transients before they reach USB transceiver ICs (e.g., TUSB2036), preserving signal integrity at 480 Mbps. Use Value: Prevents latch-up and permanent damage to USB PHYs during hot-plug events while maintaining <100 ps propagation delay. |
Use Scenario: Shielding LVDS or RGB parallel video interface lines between head unit and TFT display in automotive dashboards. IC Role / Device Role / Timing Role: Common-anode TVS array suppressing ISO 10605 ±8 kV contact discharges induced by user touch on display bezels. Use Value: Enables compliance with AEC-Q200 Grade 2 (−40°C to +105°C) without derating, due to 125°C TJ max rating. |
| Industrial Serial Communication Port | POS Terminal Keypad Interface |
|
Use Scenario: Safeguarding RS-232/RS-485 transceiver I/O pins in factory automation PLCs exposed to relay coil flyback and motor drive noise. IC Role / Device Role / Timing Role: Five-channel clamping device absorbing 8×20 µs surges up to 8.0 A peak current per line, referenced to local ground plane. Use Value: Eliminates need for external series resistors or ferrites, reducing BOM count and board space by 30% vs. discrete solutions. |
Use Scenario: ESD protection for membrane keypad scan lines and backlight control signals in retail point-of-sale terminals. IC Role / Device Role / Timing Role: Low-capacitance (80–130 pF) TVS array preventing false keypresses caused by human-body-model discharges (>8 kV). Use Value: Maintains keypad responsiveness with <0.5% signal attenuation at 1 kHz scan frequency, verified per IEC 61000-4-2 testing. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar TVS array applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SMAJ5.0A (onsemi) | Single-line SMA package; 5.0 V VRWM, 14.5 V VC @ 5 A, 400 W PPK, 150 pF | Requires 5× discrete devices for same channel count; higher capacitance limits use in >100 Mbps interfaces. | Choose when higher surge rating is needed per line and board area is not constrained. |
| TPD4E05U06DQAR (TI) | 4-line SC-70 package; 5.0 V VRWM, 12 V VC @ 4 A, 100 W PPK, 0.6 pF typical per line | Lower capacitance enables USB 3.0/PCIe Gen1; lacks fifth channel and common-anode topology for shared ground return. | Choose for ultra-high-speed interfaces where sub-1 pF capacitance is mandatory and 4-line coverage suffices. |
Compared with SMAJ5.0A and TPD4E05U06DQAR, the SMF05CT1 uniquely balances 5-line integration, 9.8 V low clamping, and SC-88 compactness - making it optimal for cost-sensitive, space-constrained USB 2.0 and automotive serial bus designs where exact 5-signal coverage is required.
Availability
SMF05CT1 is available at Aetrix Electronics and suitable for USB 2.0 interface protection, automotive infotainment display ports, and industrial serial communication ports requiring stable component supply, long-term lifecycle support, and AEC-Q200-aligned reliability.
Supply support for SMF05CT1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
onsemi (formerly ON Semiconductor) is a global semiconductor manufacturer specializing in energy-efficient power management, analog, sensing, and connectivity solutions for automotive, industrial, cloud, and consumer markets.
The SMF05CT1 belongs to onsemi's transient voltage suppressor array product line, engineered specifically for high-density, multi-line ESD and surge protection in space-constrained portable and automotive electronics.
FAQ
What is the maximum clamping voltage of the SMF05CT1 during an ESD event?
The SMF05CT1 clamps to 9.8 V at 5 A peak pulse current (8×20 µs waveform), and 12.5 V at 8 A. This ensures protected ICs-such as USB transceivers with 6.0 V absolute maximum ratings-remain within safe operating limits during IEC 61000-4-2 ESD strikes. The SMF05CT1's low clamping voltage directly reduces stress on downstream components.
Does the SMF05CT1 support automotive temperature requirements?
Yes, the SMF05CT1 operates from −40°C to +125°C junction temperature and is qualified per AEC-Q200 stress test requirements for passive components. Its SC-88 package and monolithic construction ensure mechanical and thermal stability in under-dash automotive environments, making the SMF05CT1 suitable for infotainment, telematics, and body control modules.
How many signal lines does the SMF05CT1 protect, and what is its topology?
The SMF05CT1 protects exactly five independent signal lines using a monolithic common-anode configuration: Pins 1, 3, 4, 5, and 6 are individual cathodes; Pin 2 is the shared anode. This topology allows coordinated clamping across all five lines to a single ground reference, minimizing layout complexity and avoiding ground bounce issues seen with discrete solutions.
Is the SMF05CT1 RoHS and Pb-free compliant?
Yes, the SMF05CT1 is offered in both standard and Pb-free versions (e.g., SMF05CT1G). The "G" suffix denotes lead-free termination, and the device meets RoHS Directive 2011/65/EU and JEDEC J-STD-609 Category 3 moisture sensitivity level (MSL 1). The SMF05CT1's UL 94 V-0 flammability rating further supports compliance with safety standards.
What is the typical junction capacitance of the SMF05CT1, and how does it affect high-speed signals?
The SMF05CT1 exhibits 80–130 pF junction capacitance per line (measured at 0 V, 1 MHz), which is appropriate for USB 2.0 (480 Mbps), RS-232, and SPI interfaces but unsuitable for USB 3.0 or HDMI. This capacitance introduces minimal signal rise-time degradation in sub-100 MHz applications, and the SMF05CT1's consistent CJ across channels avoids skew in parallel bus protection.
SMF05CT1 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Package/Case:
- 6-TSSOP, SC-88, SOT-363
- Series:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Type:
- Zener
- Unidirectional Channels:
- 5
- Bidirectional Channels:
- -
- Voltage - Reverse Standoff (Typ):
- 5V (Max)
- Voltage - Breakdown (Min):
- 6.2V
- Voltage - Clamping (Max) @ Ipp:
- 12.5V
- Current - Peak Pulse (10/1000µs):
- 8A (8/20µs)
- Power - Peak Pulse:
- 100W
- Power Line Protection:
- No
- Applications:
- General Purpose
- Capacitance @ Frequency:
- 80pF @ 1MHz
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- SC-88/SC70-6/SOT-363
SMF05CT1 FAQ
1.How can I place an order for SMF05CT1 through Aetrix?
Please submit a Request for Quotation (RFQ) for SMF05CT1 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SMF05CT1 reliable?
The price and inventory of SMF05CT1 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SMF05CT1 is usually 5 days.
3.What payment methods are accepted for SMF05CT1?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SMF05CT1 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SMF05CT1?
SMF05CT1 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SMF05CT1 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SMF05CT1?
For technical support, including SMF05CT1 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SMF05CT1 requirements.
6.How does Aetrix verify that SMF05CT1 is sourced from the original manufacturer or authorized distributors?
All SMF05CT1 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SMF05CT1 meets industry standards.
7.What is the process for return or replacement of SMF05CT1?
All SMF05CT1 units undergo pre-shipment inspection (PSI). If there is an issue with SMF05CT1, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SMF05CT1 part is unused and in its original packaging.
Return procedure for SMF05CT1:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SMF05CT1 Tags

-
ESD9B5.0ST5G
onsemi

-
DESD3V3E1BL-7B
Diodes Incorporated

-
ESD5Z3.3T1G
onsemi

-
D5V0H1B2LP-7B
Diodes Incorporated

-
D5V0P1B2LP-7B
Diodes Incorporated

-
DESD5V0U1BA-7
Diodes Incorporated

-
ESD5Z5.0T1G
onsemi

-
DESD5V0U1BB-7
Diodes Incorporated

-
D12V0L1B2LP-7B
Diodes Incorporated

-
PESD2V0Y1BSFYL
Nexperia USA Inc.

-
DF2S5M4CT,L3F
Toshiba Semiconductor and Storage

-
D5V0L1B2WS-7
Diodes Incorporated
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

