Vishay Siliconix SQJ912DEP-T1_GE3
- Part No.:
- SQJ912DEP-T1_GE3
- Manufacturer:
- Vishay Siliconix
- Category:
- FET, MOSFET Arrays
- Package:
- PowerPAK® SO-8 Dual
- Datasheet:
-
SQJ912DEP-T1_GE3.pdf
- Description:
- MOSFET 2N-CH 40V 30A PPAK SO8
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SQJ912DEP-T1_GE3 from Vishay Siliconix is an automotive-grade dual N-channel TrenchFET® MOSFET rated for 40 V (D–S), 175 °C junction operation, with RDS(on) = 7.3 mΩ at VGS = 10 V and 10.2 mΩ at VGS = 4.5 V per channel, delivering 30 A continuous drain current per leg in PowerPAK® SO-8L package - used in high-reliability DC–DC converters and motor control stages in engine management systems.
For engineers reviewing the SQJ912DEP-T1_GE3 datasheet, SQJ912DEP-T1_GE3 pinout, SQJ912DEP-T1_GE3 application, or SQJ912DEP-T1_GE3 equivalent, this page delivers verified thermal ratings (RthJC = 5.5 °C/W), AEC-Q101 qualification status, dual-channel gate drive compatibility, and body diode recovery metrics (Qrr = 16–32 nC) critical for synchronous rectification and H-bridge design validation.
Technical Context
This dual N-channel MOSFET integrates two independent 40 V, 30 A channels in a single leadless PowerPAK SO-8L package with exposed-drain thermal pads on both sides. Its trench-based silicon structure enables low RDS(on) across temperature and robust UIS performance, supported by 100 % Rg and avalanche testing per unit.
The device operates over –55 °C to +175 °C junction range and is qualified to AEC-Q101 Rev. D. Gate threshold voltage (1.5–2.5 V) and low Qg (24–36 nC) enable fast switching with standard 3.3 V/5 V logic-level drivers while maintaining stable conduction under high ambient conditions typical in powertrain subsystems.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VDS | 40 V - Maximum blocking voltage before avalanche onset; defines safe operating range in 12 V/24 V automotive battery-fed circuits. |
| RDS(on) @ VGS = 10 V | 7.3 mΩ - Enables ≤2.2 W conduction loss at 30 A per channel, reducing heatsink requirements in space-constrained modules. |
| RDS(on) @ VGS = 4.5 V | 10.2 mΩ - Ensures reliable turn-on with 5 V microcontroller GPIO or gate driver outputs without level-shifting. |
| ID (continuous, per leg) | 30 A at TC = 25 °C - Supports high-current half-bridge legs in EPS or HVAC blower inverters with PCB-mounted thermal relief. |
| Qg (total gate charge) | 24–36 nC - Determines required gate driver peak current (e.g., ≥3.6 A for 10 ns rise time); impacts switching loss trade-off. |
| TJ max | +175 °C - Enables placement near hot zones (e.g., under-hood ECUs) without derating below full current rating. |
| EAS | 18 mJ - Specifies single-pulse avalanche energy handling; validates ruggedness against inductive kickback in solenoid drivers. |
Pinout & Package
Package: PowerPAK® SO-8L (dual-channel, leadless, thermally enhanced). Dimensions: 6.15 mm × 5.13 mm × 1.07 mm (L × W × H), with exposed copper drain pads on bottom side for direct PCB thermal coupling.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (S1) | Source of Channel 1 | Low-side return path for first MOSFET; tied to PCB ground plane for minimal loop inductance. |
| 2 (G1) | Gate of Channel 1 | Control input for first channel; requires <100 nA leakage budget and 2.8 Ω typical gate resistance. |
| 3 (S2) | Source of Channel 2 | Independent source node for second channel; enables floating high-side or dual low-side configurations. |
| 4 (G2) | Gate of Channel 2 | Isolated gate terminal allowing independent PWM control of each channel without crosstalk. |
| D1 / D2 (exposed pad) | Drain terminals (both channels) | Shared thermal and electrical drain connection; soldered directly to large copper pour for RthJC = 5.5 °C/W. |
Key Features
| Feature | Design Value |
|---|---|
| AEC-Q101 qualified | Validated for automotive applications per stress test requirements including HTOL, TC, UHAST, and ESD - supports ASIL-B system integration without additional qualification effort. |
| 100 % Rg and UIS tested | Each unit undergoes individual gate resistance screening and unclamped inductive switching stress - guarantees robustness in real-world load dump or short-circuit events. |
| Low Qgd/Qgs ratio | Qgd ≈ 5 nC, Qgs ≈ 5 nC - minimizes Miller plateau duration and improves immunity to dv/dt-induced false turn-on in high-speed switching. |
| Body diode trr = 25–50 ns | Fast reverse recovery enables use in synchronous rectification without external Schottky catch diodes - reduces BOM count and conduction loss in buck converters. |
| Thermally optimized PowerPAK SO-8L | RthJA = 85 °C/W (PCB mount), RthJC = 5.5 °C/W - allows >2× power density vs. standard SO-8 while maintaining 175 °C operation. |
Applications
| Engine Control Unit (ECU) Fuel Injector Driver | Electric Power Steering (EPS) Motor Phase Switch |
|---|---|
Use Scenario: High-speed, high-current switching of 12 V fuel injectors with precise pulse-width modulation. IC Role / Device Role / Timing Role: Dual-channel low-side switch controlling paired injectors; one channel per injector bank with independent gate timing. Use Value: 7.3 mΩ RDS(on) limits resistive heating during 10 ms pulses; 175 °C rating ensures reliability near hot engine components. |
Use Scenario: Half-bridge phase-leg switching in 24 V EPS motor inverter with regenerative braking. IC Role / Device Role / Timing Role: Dual N-channel configuration used as low-side switches in three-phase inverter; synchronized with high-side gate drivers. Use Value: Fast 25–50 ns body diode trr and low Qrr reduce shoot-through risk and conduction loss during freewheeling. |
| Onboard Charger (OBC) Primary-Side Synchronous Rectifier | 12 V DC–DC Converter for ADAS Camera Module |
Use Scenario: Secondary-side synchronous rectification in isolated 3.3 kW OBC LLC resonant converter. IC Role / Device Role / Timing Role: Dual-channel MOSFET replacing Schottky diodes; each channel handles one transformer secondary winding. Use Value: 10.2 mΩ RDS(on) at 4.5 V enables direct drive from LLC controller's 5 V gate outputs - eliminates gate driver ICs and saves board area. |
Use Scenario: Compact, high-efficiency 12 V to 3.3 V step-down converter powering vision processing SoCs in rear-view cameras. IC Role / Device Role / Timing Role: Dual N-channel used in multiphase buck topology - one channel per phase with interleaved PWM. Use Value: 30 A per leg supports >15 A total output with <15 mΩ effective DCR; 175 °C rating permits sealed enclosure mounting without airflow. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual N-channel automotive MOSFET applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| IRF7341TRPBF | RDS(on) = 24 mΩ @ 10 V; TO-252 package; not AEC-Q101 qualified; RthJC = 3.5 °C/W but larger footprint. | Limited to non-safety-critical industrial DC–DC; lacks automotive qualification and thermal density. | Select only for cost-sensitive non-automotive designs where 175 °C operation and AEC-Q101 are unnecessary. |
| DMTH4007LPSQ-13 | RDS(on) = 6.5 mΩ @ 10 V; same PowerPAK SO-8L; AEC-Q101 qualified; slightly lower VDS (40 V nominal, 45 V max). | Compatible in identical PCB layout; better RDS(on) but narrower safe operating area above 40 V. | Prefer for new designs requiring marginally lower conduction loss; verify 40 V system transients do not exceed 45 V absolute max. |
Compared with IRF7341TRPBF and DMTH4007LPSQ-13, SQJ912DEP-T1_GE3 offers balanced trade-offs: AEC-Q101 compliance and 175 °C rating unmatched by IRF7341TRPBF, and wider 40 V VDS rating than DMTH4007LPSQ-13's 45 V max - making it optimal for 12 V/24 V automotive systems with strict transient immunity requirements.
Availability
SQJ912DEP-T1_GE3 is available at Aetrix Electronics and suitable for engine control units, electric power steering systems, and onboard chargers requiring stable component supply across extended automotive production lifecycles.
Supply support for SQJ912DEP-T1_GE3 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Vishay Siliconix designs and manufactures high-performance discrete semiconductors, specializing in power MOSFETs, diodes, and optoelectronics with emphasis on automotive, industrial, and computing applications.
The SQJ912DEP-T1_GE3 belongs to Vishay's TrenchFET® Gen IV automotive MOSFET family, engineered specifically for high-temperature, high-reliability power switching in engine bay and chassis-mounted electronic control modules.
FAQ
What is the maximum continuous drain current per channel for SQJ912DEP-T1_GE3 at 125 °C case temperature?
The SQJ912DEP-T1_GE3 supports 26 A continuous drain current per channel at TC = 125 °C, as specified in its Absolute Maximum Ratings table. This derating reflects thermal limitations of the PowerPAK SO-8L package and must be applied when ambient or board temperatures exceed 25 °C - SQJ912DEP-T1_GE3 maintains full 30 A rating only at TC = 25 °C.
Does SQJ912DEP-T1_GE3 support logic-level gate drive from a 3.3 V microcontroller?
SQJ912DEP-T1_GE3 has a gate threshold voltage range of 1.5–2.5 V, enabling turn-on with 3.3 V logic; however, its RDS(on) rises to 10.2 mΩ at VGS = 4.5 V and is not characterized below that. For reliable 3.3 V drive, external gate boosting or level-shifting is recommended - SQJ912DEP-T1_GE3 is optimized for 4.5 V and higher gate voltages.
Is SQJ912DEP-T1_GE3 pin-compatible with other PowerPAK SO-8L dual MOSFETs like SQJ852EP?
SQJ912DEP-T1_GE3 uses the standard PowerPAK SO-8L dual footprint with pin 1 = S1, pin 2 = G1, pin 3 = S2, pin 4 = G2, and shared drain pads - matching SQJ852EP and similar Vishay duals. However, SQJ912DEP-T1_GE3 is not a drop-in replacement due to differences in RDS(on), Qg, and thermal resistance; PCB layout is compatible but circuit validation is required - SQJ912DEP-T1_GE3 must be re-characterized in target application.
What is the body diode forward voltage of SQJ912DEP-T1_GE3 at 7 A and room temperature?
The body diode forward voltage (VSD) of SQJ912DEP-T1_GE3 is specified as 0.79–1.2 V at IF = 7 A and VGS = 0 V, measured at TA = 25 °C. This parameter is critical for freewheeling efficiency in H-bridge and synchronous rectifier topologies - SQJ912DEP-T1_GE3's low VSD contributes to reduced conduction loss compared to discrete Schottky solutions.
How is the thermal performance of SQJ912DEP-T1_GE3 validated for automotive under-hood environments?
SQJ912DEP-T1_GE3 is qualified to AEC-Q101 and rated for TJ = –55 to +175 °C, with RthJC = 5.5 °C/W measured on FR4 PCB. Its thermal capability is validated via high-temperature operating life (HTOL) testing at 175 °C for 1000 hours and thermal cycling (–55 °C to +175 °C) - SQJ912DEP-T1_GE3 meets all requirements for under-hood placement without forced cooling.
SQJ912DEP-T1_GE3 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Vishay Siliconix
- Series:
- TrenchFET®
- Package/Case:
- PowerPAK® SO-8 Dual
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Technology:
- MOSFET (Metal Oxide)
- Configuration:
- 2 N-Channel (Dual)
- FET Feature:
- -
- Drain to Source Voltage (Vdss):
- 40V
- Current - Continuous Drain (Id) @ 25°C:
- 30A (Tc)
- Rds On (Max) @ Id, Vgs:
- 7.3mOhm @ 7A, 10V
- Vgs(th) (Max) @ Id:
- 2.5V @ 250µA
- Gate Charge (Qg) (Max) @ Vgs:
- 36nC @ 10V
- Input Capacitance (Ciss) (Max) @ Vds:
- -
- Power - Max:
- 27W (Tc)
- Operating Temperature:
- -55°C ~ 175°C (TJ)
- Grade:
- Automotive
- Qualification:
- AEC-Q101
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- PowerPAK® SO-8 Dual
SQJ912DEP-T1_GE3 FAQ
1.How can I place an order for SQJ912DEP-T1_GE3 through Aetrix?
Please submit a Request for Quotation (RFQ) for SQJ912DEP-T1_GE3 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SQJ912DEP-T1_GE3 reliable?
The price and inventory of SQJ912DEP-T1_GE3 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SQJ912DEP-T1_GE3 is usually 5 days.
3.What payment methods are accepted for SQJ912DEP-T1_GE3?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SQJ912DEP-T1_GE3 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SQJ912DEP-T1_GE3?
SQJ912DEP-T1_GE3 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SQJ912DEP-T1_GE3 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SQJ912DEP-T1_GE3?
For technical support, including SQJ912DEP-T1_GE3 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SQJ912DEP-T1_GE3 requirements.
6.How does Aetrix verify that SQJ912DEP-T1_GE3 is sourced from the original manufacturer or authorized distributors?
All SQJ912DEP-T1_GE3 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SQJ912DEP-T1_GE3 meets industry standards.
7.What is the process for return or replacement of SQJ912DEP-T1_GE3?
All SQJ912DEP-T1_GE3 units undergo pre-shipment inspection (PSI). If there is an issue with SQJ912DEP-T1_GE3, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SQJ912DEP-T1_GE3 part is unused and in its original packaging.
Return procedure for SQJ912DEP-T1_GE3:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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