STMicroelectronics STS19N3LLH6
- Part No.:
- STS19N3LLH6
- Manufacturer:
- STMicroelectronics
- Category:
- FETs, MOSFETs
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
STS19N3LLH6.pdf
- Description:
- MOSFET N-CH 30V 19A 8SO
- Quantity:
- Payment:

- Shipping:

Inventory:8,264
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
STS19N3LLH6 from STMicroelectronics is an N-channel 30 V, 19 A Power MOSFET in SO-8 package featuring 4.9 mΩ RDS(on) at VGS = 10 V, 17 nC total gate charge, and high avalanche ruggedness. It serves as a low-loss main or synchronous rectifier switch in DC-DC converters, motor drivers, and load switches operating up to 100 °C case temperature.
For engineers reviewing the STS19N3LLH6 datasheet, STS19N3LLH6 pinout, STS19N3LLH6 application, or STS19N3LLH6 equivalent, key selection criteria include RDS(on) vs. gate drive voltage (4.5 V/10 V), pulsed current capability (76 A), thermal resistance (47 °C/W on FR-4), and SO-8 footprint compatibility with existing board layouts.
Technical Context
This MOSFET implements ST's STripFET™ VI DeepGATE™ architecture, combining optimized cell pitch and a reinforced gate structure to minimize RDS(on) × Qg figure-of-merit. Its 1690 pF input capacitance and 290 pF reverse transfer capacitance support fast switching at 4.5 V logic-level drive.
The device integrates a robust intrinsic body diode with 14 ns reverse recovery time and 16.8 nC Qrr at 150 °C junction temperature, enabling efficient hard-switched and synchronous rectification topologies without external Schottky supplementation.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VDS | 30 V - Maximum drain-source blocking voltage for 12–24 V system rails |
| RDS(on) @ 10 V | 4.9 mΩ - Enables ≤1.8 W conduction loss at 19 A continuous current |
| Qg | 17 nC - Low gate drive energy supports 1 MHz+ switching with <1 W driver loss |
| ID (TC=100°C) | 11.8 A - Sustained current rating under thermally constrained PCB conditions |
| tr/tf | 9.5 ns / 12 ns - Fast edge rates reduce switching transition losses in buck/boost stages |
| Qrr | 16.8 nC - Predictable diode recovery behavior enables reliable synchronous FET timing control |
| Rthj-amb | 47 °C/W - Thermal performance measured on 1 in² FR-4 board, 2 oz Cu, defines heatsink-free power ceiling |
Pinout & Package
STS19N3LLH6 is housed in a standard SO-8 surface-mount package (ECOPACK® compliant) with exposed drain pad for enhanced thermal dissipation. Pin numbering follows JEDEC MS-012AC outline.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 2, 3, 4, 5, 7, 8 | Drain (D) | Internally paralleled terminals connected to exposed thermal pad - primary current path and heat sink interface |
| 6 | Source (S) | Low-side return node; referenced for gate drive and current sensing |
| G | Gate (G) | Control terminal requiring ≤±20 V bias; 1.7 Ω gate resistance limits ringing during fast transitions |
Key Features
| Feature | Design Value |
|---|---|
| RDS(on) × Qg benchmark | 83 mΩ·nC - Industry-leading conduction–switching trade-off for 30 V logic-level MOSFETs |
| High avalanche ruggedness | Unclamped inductive switching rated per JEDEC JESD22-A109 - supports robust overvoltage transient handling |
| Low gate drive power loss | Qg = 17 nC at VDD = 15 V enables <0.5 W average gate drive power at 500 kHz |
| DeepGATE™ gate structure | Reduces gate-to-drain coupling (Crss = 290 pF), improving Miller immunity in high-dV/dt environments |
| SO-8 thermal pad | Exposed drain pad provides direct thermal path to PCB copper - critical for maintaining TJ < 150 °C at full load |
Applications
| DC-DC Buck Converter | Brushed DC Motor Driver |
|---|---|
Use Scenario: High-efficiency 12 V input to 3.3/5/12 V output step-down converter in industrial PLC I/O modules. IC Role / Device Role: Synchronous rectifier FET replacing Schottky diode to reduce conduction loss and improve light-load efficiency. Use Value: 4.9 mΩ RDS(on) cuts rectifier loss by >60% vs. 40 V Schottky, enabling >95% peak efficiency at 10 A output. | Use Scenario: H-bridge driver for 24 V, 10 A brushed motors in automated gate actuators and HVAC dampers. IC Role / Device Role: Low-side switch controlling motor direction and PWM speed regulation. Use Value: 76 A pulsed current rating handles 6× stall current surges; 14 ns trr prevents shoot-through during bridge commutation. |
| Hot-Swap Controller | Load Switch for Server PSU Rails |
Use Scenario: Inrush-limited 12 V hot-swap circuit protecting backplane slots in telecom line cards. IC Role / Device Role: Main pass element with external gate driver managing controlled turn-on slew rate. Use Value: 11.8 A continuous rating at 100 °C case ensures stable operation during sustained 10 A loads; low Qg enables precise dV/dt control. | Use Scenario: OR-ing and sequencing switch for redundant 12 V server power supply outputs. IC Role / Device Role: Back-to-back configured N-channel MOSFET providing bidirectional blocking and low-loss conduction. Use Value: 30 V VDS withstands 12 V rail transients; 4.9 mΩ RDS(on) limits voltage drop to <60 mV at 12 A, minimizing bus droop. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar N-channel logic-level power MOSFET applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| IRLML6344TRPBF | RDS(on) = 5.5 mΩ @ 4.5 V; Qg = 11.5 nC; SO-8 package | Lower gate charge improves 4.5 V drive efficiency but higher RDS(on) increases conduction loss above 8 A | Prefer when gate drive is strictly 3.3–4.5 V and peak current ≤8 A |
| DMN3028LSD-13 | RDS(on) = 3.2 mΩ @ 10 V; Qg = 22 nC; SO-8 package with dual die | Lower RDS(on) reduces conduction loss but higher Qg demands stronger gate driver and increases switching loss | Prefer when thermal margin is tight and gate drive can support ≥2 A peak current |
Compared with IRLML6344TRPBF and DMN3028LSD-13, STS19N3LLH6 delivers optimal balance of low RDS(on), moderate Qg, and proven avalanche capability-making it preferred for 12–24 V systems requiring reliability under overload and transient stress.
Availability
STS19N3LLH6 is available at Aetrix Electronics and suitable for DC-DC converters, motor drivers, hot-swap controllers, and server load switches requiring stable component supply across industrial, telecom, and embedded computing programs.
Supply support for STS19N3LLH6 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power devices, sensors, and analog ICs for industrial, automotive, and consumer markets.
STS19N3LLH6 belongs to ST's STripFET™ VI DeepGATE™ power MOSFET product line, engineered specifically for high-efficiency, high-reliability switching in space-constrained 12–24 V power conversion and motor control applications.
FAQ
Is STS19N3LLH6 suitable for 3.3 V logic-level gate drive?
No. While STS19N3LLH6 specifies RDS(on) = 6.6 mΩ at VGS = 4.5 V, its gate threshold voltage (VGS(th)) ranges from 1.0 to 2.5 V, and full enhancement requires ≥4.5 V for acceptable conduction loss. Driving from 3.3 V results in RDS(on) >15 mΩ and excessive heating at >5 A. Use only with 4.5 V or higher gate drive.
What is the maximum safe operating area (SOA) for single-pulse unclamped inductive switching?
The SOA curve (Figure 2) confirms 76 A pulsed drain current is sustainable for ≤10 µs at VDS = 30 V and TJ = 25 °C. At 100 °C junction temperature, the limit drops to ~45 A for the same pulse width. Derating is required for repetitive pulses or elevated ambient temperatures per Figure 2's logarithmic boundaries.
Does STS19N3LLH6 have integrated ESD protection on the gate?
Yes. The gate oxide is protected by internal Zener clamping, evidenced by ±100 nA gate leakage (IGSS) at ±20 V and no gate rupture observed up to the absolute maximum VGS rating of ±20 V. However, external gate resistors (≥10 Ω) and TVS diodes are still recommended in high-noise environments per ST application note AN4107.
Can STS19N3LLH6 be used in parallel configurations?
Yes, but with strict layout and gate drive matching. Its positive temperature coefficient of RDS(on) (Figure 11) enables current sharing, yet mismatched gate loop inductance or trace resistance causes dynamic imbalance. ST recommends individual 10 Ω gate resistors, symmetrical PCB routing, and Kelvin source connections to ensure balanced turn-on/turn-off across paralleled units.
STS19N3LLH6 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- DeepGATE™, STripFET™ VI
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- FET Type:
- N-Channel
- Technology:
- MOSFET (Metal Oxide)
- Drain to Source Voltage (Vdss):
- 30 V
- Current - Continuous Drain (Id) @ 25°C:
- 19A (Tc)
- Drive Voltage (Max Rds On, Min Rds On):
- 4.5V, 10V
- Rds On (Max) @ Id, Vgs:
- 5.6mOhm @ 9.5A, 10V
- Vgs(th) (Max) @ Id:
- 1V @ 250µA
- Gate Charge (Qg) (Max) @ Vgs:
- 17 nC @ 15 V
- Vgs (Max):
- ±20V
- Input Capacitance (Ciss) (Max) @ Vds:
- 1690 pF @ 25 V
- FET Feature:
- -
- Power Dissipation (Max):
- 2.7W (Ta)
- Operating Temperature:
- -55°C ~ 150°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
STS19N3LLH6 FAQ
1.How can I place an order for STS19N3LLH6 through Aetrix?
Please submit a Request for Quotation (RFQ) for STS19N3LLH6 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for STS19N3LLH6 reliable?
The price and inventory of STS19N3LLH6 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STS19N3LLH6 is usually 5 days.
3.What payment methods are accepted for STS19N3LLH6?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for STS19N3LLH6 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for STS19N3LLH6?
STS19N3LLH6 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your STS19N3LLH6 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for STS19N3LLH6?
For technical support, including STS19N3LLH6 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STS19N3LLH6 requirements.
6.How does Aetrix verify that STS19N3LLH6 is sourced from the original manufacturer or authorized distributors?
All STS19N3LLH6 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STS19N3LLH6 meets industry standards.
7.What is the process for return or replacement of STS19N3LLH6?
All STS19N3LLH6 units undergo pre-shipment inspection (PSI). If there is an issue with STS19N3LLH6, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The STS19N3LLH6 part is unused and in its original packaging.
Return procedure for STS19N3LLH6:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
STS19N3LLH6 Tags

-
BSZ180P03NS3EGATMA1
Infineon Technologies

-
SIRA14DP-T1-GE3
Vishay Siliconix

-
AO4419
Alpha & Omega Semiconductor Inc.

-
SISA14BDN-T1-GE3
Vishay Siliconix

-
PSMN9R5-30YLC,115
Nexperia USA Inc.

-
BUK9Y21-40E,115
Nexperia USA Inc.

-
RTQ035N03HZGTR
Rohm Semiconductor

-
FDMS7680
onsemi

-
RQ3E180BNTB
Rohm Semiconductor

-
STL6N2VH5
STMicroelectronics

-
DMPH4029LFGQ-7
Diodes Incorporated

-
DMT6015LSS-13
Diodes Incorporated
Tech Hub
Comparator circuit design covering voltage thresholds, input limits, open-collector outputs, LM393 wiring, op-amp differences, hysteresis, timing, window detection and practical fault diagnosis.
Schmitt triggers use separate rising and falling thresholds to stabilize slow or noisy signals. This guide covers hysteresis, 74HC14 and 74HCT14 selection, comparator calculations, RC oscillators and p…
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

