onsemi SZMA3075WALT1G
- Part No.:
- SZMA3075WALT1G
- Manufacturer:
- onsemi
- Category:
- TVS Diodes
- Package:
- TO-236-3, SC-59, SOT-23-3
- Datasheet:
-
SZMA3075WALT1G.pdf
- Description:
- TVS DIODE 6.5VWM SOT23-3
- Quantity:
- Payment:

- Shipping:

Inventory:9,071
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SZMA3075WALT1G from onsemi is a dual common-anode Zener ESD protection diode in SOT-23 package, rated for 7.2–7.9 V zener voltage at 5 mA, 80 pF typical capacitance at 0 V/1 MHz, and 16 kV HBM / 30 kV IEC 61000-4-2 ESD protection. It protects two signal lines in space-constrained interfaces such as USB data lines or low-voltage sensor I/O.
For engineers reviewing the SZMA3075WALT1G datasheet, pinout, applications, or equivalent options, key selection criteria include dual-line unidirectional clamping capability, low leakage (<1 nA @ 5 V), AEC-Q101 qualification, and SOT-23 footprint compatibility with automated assembly.
Technical Context
This device integrates two monolithic silicon Zener junctions sharing a common anode terminal (Pin 3), enabling independent reverse-biased clamping of two separate signal paths. Its design targets transient overvoltage suppression in low-capacitance, high-speed digital interfaces where board area is constrained.
The dual Zener structure delivers symmetrical breakdown behavior (7.2–7.9 V @ 5 mA) with low dynamic impedance (6–15 Ω @ 5 mA) and minimal parasitic capacitance (80 pF typ @ 0 V, 1 MHz), supporting signal integrity in 10–100 Mbps data lines while meeting stringent ESD immunity requirements (30 kV air/contact discharge).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Zener Voltage | 7.2–7.9 V @ 5 mA - defines clamping threshold for overvoltage protection on two independent lines |
| Capacitance | 80 pF typical @ 0 V, 1 MHz - ensures minimal signal distortion on high-speed data lines (e.g., USB 2.0) |
| ESD Rating | 30 kV contact & air discharge per IEC 61000-4-2 - exceeds industrial and automotive interface immunity requirements |
| Leakage Current | <1 nA @ 5 V reverse bias - prevents loading of high-impedance sensor or reference circuits |
| Package | SOT-23 (Case 318, Style 12) - 2.90 × 1.30 × 1.00 mm surface-mount footprint compatible with standard pick-and-place equipment |
| Thermal Resistance | 556 °C/W junction-to-ambient - supports 225 mW steady-state dissipation on FR-5 board with derating above 25°C |
Pinout & Package
SOT-23 package (Case 318, Style 12) with gull-wing leads, Pb-free, halogen-free, RoHS-compliant construction. Void-free transfer-molded thermosetting plastic case optimized for automated board assembly.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| Pin 1 | Cathode (Line 1) | Reverse-biased terminal for first protected signal line; connects to I/O trace requiring clamping |
| Pin 2 | Cathode (Line 2) | Reverse-biased terminal for second protected signal line; enables dual-line protection in single footprint |
| Pin 3 | Anode (Common) | Shared reference node tied to system ground or supply rail; establishes common clamping reference point |
Key Features
| Feature | Design Value |
|---|---|
| Dual common-anode Zener topology | Enables independent ESD clamping of two signal lines using one SOT-23 footprint, reducing PCB area by ~50% vs. discrete diodes |
| Low 80 pF capacitance | Maintains signal rise/fall times & bandwidth in 480 Mbps USB 2.0 and similar high-speed interfaces |
| AEC-Q101 qualification | Validated for automotive-grade reliability including temperature cycling, HTOL, and ESD stress under controlled manufacturing site conditions |
| 16 kV HBM / 30 kV IEC ESD rating | Exceeds IEC 61000-4-2 Level 4 requirements, eliminating need for external TVS stages in many industrial port designs |
Applications
| USB 2.0 Data Lines | Automotive Sensor Interfaces |
|---|---|
Use Scenario: Protecting D+ and D− lines of USB 2.0 ports against ESD events during hot-plug insertion. IC Role / Device Role / Timing Role: Dual-line bidirectional transient voltage suppressor with common-ground reference. Use Value: Prevents latch-up or damage to USB transceivers while maintaining <100 ps signal delay and <0.1 dB insertion loss at 480 MHz. |
Use Scenario: Shielding LIN bus or analog sensor outputs (e.g., pressure, temperature) in engine control modules from load-dump and ESD transients. IC Role / Device Role / Timing Role: Low-leakage Zener clamp referenced to chassis ground, operating across −40°C to +125°C ambient. Use Value: Ensures signal integrity during ISO 7637-2 pulse 1/2a/5a tests without degrading 12-bit ADC resolution or introducing offset drift. |
| Industrial Serial Interfaces | Medical Equipment I/O Ports |
Use Scenario: Safeguarding RS-485 transceiver inputs/outputs in factory automation controllers exposed to cable-induced surges. IC Role / Device Role / Timing Role: Unidirectional clamping diode pair with matched breakdown voltage and low dynamic impedance. Use Value: Limits transient overshoot to <12 V during 1 kV/500 A surge events, preserving transceiver functional safety per IEC 61000-4-4 Level 3. |
Use Scenario: Protecting patient-connected ECG or SpO₂ sensor inputs from operator-handling ESD in diagnostic devices. IC Role / Device Role / Timing Role: High-reliability, low-capacitance ESD suppressor compliant with IEC 60601-1-2 4th edition. Use Value: Delivers 30 kV contact discharge immunity without compromising sub-μV noise floor or DC accuracy of medical front-end amplifiers. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-Zener ESD protection applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ESD5Z7.0T5G | Single-channel, 7.0 V nominal VZ, 100 pF capacitance, same SOT-23 package | Requires two devices for dual-line protection; higher capacitance may limit >100 Mbps data rates | Select when board layout allows duplication or when tighter VZ tolerance (±5%) is required over MA3075W series |
| CM1213A-04SO | Quad-channel, 5.5 V VRWM, 0.6 pF per channel, SOIC-8 package | Lower capacitance ideal for USB 3.0/PCIe; larger footprint and different mounting process | Prefer for multi-line, ultra-high-speed interfaces where 0.6 pF is mandatory and space permits SOIC-8 placement |
Compared with ESD5Z7.0T5G and CM1213A-04SO, SZMA3075WALT1G uniquely balances dual-line integration, 80 pF capacitance, and AEC-Q101 compliance in the smallest possible footprint-making it optimal for space-constrained automotive and industrial I/O where two signals require coordinated clamping.
Availability
SZMA3075WALT1G is available at Aetrix Electronics and suitable for USB 2.0 interface protection, automotive LIN bus safeguarding, and industrial RS-485 port hardening requiring stable component supply and long-term lifecycle support.
Supply support for SZMA3075WALT1G includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
onsemi (Semiconductor Components Industries, LLC) is a global semiconductor supplier delivering energy-efficient, intelligent power and sensing solutions for automotive, industrial, cloud, medical, and IoT applications.
SZMA3075WALT1G belongs to onsemi's Zener-based ESD protection portfolio, engineered specifically for compact, high-reliability transient suppression in automotive and industrial signal interfaces where AEC-Q101 validation and minimal board area are critical.
FAQ
What is the exact pin configuration of SZMA3075WALT1G?
SZMA3075WALT1G uses SOT-23 package Style 12: Pin 1 is Cathode for Line 1, Pin 2 is Cathode for Line 2, and Pin 3 is the Common Anode. This dual-cathode/common-anode arrangement enables independent clamping of two signal paths with shared ground reference, as confirmed in the official onsemi datasheet MA3075WALT1/D Rev. 5.
Is SZMA3075WALT1G suitable for automotive applications?
Yes, SZMA3075WALT1G is AEC-Q101 qualified and PPAP capable, with the "SZ" prefix indicating automotive-grade manufacturing controls and site-specific change management. It operates across −55°C to +150°C junction temperature and meets ISO 10605 ESD requirements-making SZMA3075WALT1G appropriate for engine control, body electronics, and ADAS sensor interfaces.
What is the maximum steady-state power dissipation for SZMA3075WALT1G?
SZMA3075WALT1G has a steady-state power dissipation rating of 225 mW at 25°C ambient, derating linearly at 1.8 mW/°C above that temperature when mounted on an FR-5 board (1.0 × 0.75 × 0.062 in). This thermal performance is validated in the Maximum Ratings table of the official onsemi datasheet.
Does SZMA3075WALT1G meet RoHS and halogen-free requirements?
Yes, SZMA3075WALT1G is Pb-free, halogen-free/BFR-free, and fully RoHS compliant, as explicitly stated in the Features section of the onsemi datasheet. The "G" suffix and marking "7W5 M" confirm its Pb-free packaging and environmental compliance status.
What is the typical capacitance of SZMA3075WALT1G and at what test condition?
The typical capacitance of SZMA3075WALT1G is 80 pF, measured at 0 V reverse bias and 1 MHz frequency, as specified in the Electrical Characteristics table. This low value supports signal integrity in high-speed digital interfaces like USB 2.0 while maintaining effective ESD clamping performance.
SZMA3075WALT1G Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Package/Case:
- TO-236-3, SC-59, SOT-23-3
- Series:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Type:
- Zener
- Unidirectional Channels:
- 2
- Bidirectional Channels:
- -
- Voltage - Reverse Standoff (Typ):
- 6.5V
- Voltage - Breakdown (Min):
- 7.2V
- Voltage - Clamping (Max) @ Ipp:
- -
- Current - Peak Pulse (10/1000µs):
- -
- Power - Peak Pulse:
- 15W
- Power Line Protection:
- No
- Applications:
- -
- Capacitance @ Frequency:
- 80pF @ 1MHz
- Operating Temperature:
- -55°C ~ 150°C (TJ)
- Grade:
- Automotive
- Qualification:
- AEC-Q101
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- SOT-23-3 (TO-236)
SZMA3075WALT1G FAQ
1.How can I place an order for SZMA3075WALT1G through Aetrix?
Please submit a Request for Quotation (RFQ) for SZMA3075WALT1G on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SZMA3075WALT1G reliable?
The price and inventory of SZMA3075WALT1G are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SZMA3075WALT1G is usually 5 days.
3.What payment methods are accepted for SZMA3075WALT1G?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SZMA3075WALT1G transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SZMA3075WALT1G?
SZMA3075WALT1G orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SZMA3075WALT1G order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SZMA3075WALT1G?
For technical support, including SZMA3075WALT1G datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SZMA3075WALT1G requirements.
6.How does Aetrix verify that SZMA3075WALT1G is sourced from the original manufacturer or authorized distributors?
All SZMA3075WALT1G products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SZMA3075WALT1G meets industry standards.
7.What is the process for return or replacement of SZMA3075WALT1G?
All SZMA3075WALT1G units undergo pre-shipment inspection (PSI). If there is an issue with SZMA3075WALT1G, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SZMA3075WALT1G part is unused and in its original packaging.
Return procedure for SZMA3075WALT1G:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SZMA3075WALT1G Tags

-
ESD9B5.0ST5G
onsemi

-
DESD3V3E1BL-7B
Diodes Incorporated

-
ESD5Z3.3T1G
onsemi

-
D5V0H1B2LP-7B
Diodes Incorporated

-
D5V0P1B2LP-7B
Diodes Incorporated

-
DESD5V0U1BA-7
Diodes Incorporated

-
ESD5Z5.0T1G
onsemi

-
DESD5V0U1BB-7
Diodes Incorporated

-
D12V0L1B2LP-7B
Diodes Incorporated

-
PESD2V0Y1BSFYL
Nexperia USA Inc.

-
DF2S5M4CT,L3F
Toshiba Semiconductor and Storage

-
D5V0L1B2WS-7
Diodes Incorporated
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

