onsemi SZNUP2201MR6T1G
- Part No.:
- SZNUP2201MR6T1G
- Manufacturer:
- onsemi
- Category:
- TVS Diodes
- Package:
- SOT-23-6 Thin, TSOT-23-6
- Datasheet:
-
SZNUP2201MR6T1G.pdf
- Description:
- ESD / SURGE PROTECTOR
- Quantity:
- Payment:

- Shipping:

Inventory:6,232
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Product details
Overview
SZNUP2201MR6T1G from onsemi is a low-capacitance, unidirectional ESD protection diode array in TSOP-6 package, designed to protect two high-speed data lines against IEC 61000-4-2 Level 4 ESD (±20 kV contact), with 5 V working peak reverse voltage, 12.5 V clamping voltage at 5 A, and 3.0–5.0 pF junction capacitance between I/O and GND.
For engineers reviewing the SZNUP2201MR6T1G datasheet, pinout, applications, or equivalent options, this device serves as a compact, AEC-Q101-qualified solution for USB 2.0, DVI, and flat-panel display interface protection where low signal distortion and fast transient response are critical.
Technical Context
The SZNUP2201MR6T1G integrates two steering diodes and one surge protection diode in a single TSOP-6 package, enabling bidirectional clamping of two I/O lines to either VCC (pin 5) or ground (pin 2). Its unidirectional architecture supports fixed-reference clamping with VRWM = 5 V and VBR = 6.0 V (IT = 1 mA).
Clamping behavior follows IEC 61000-4-2 waveform compliance, delivering VC = 12.5 V @ IPP = 5 A and VC = 20 V @ IPP = 8 A, while maintaining low parasitic capacitance (1.5–3.0 pF between I/O pins) to preserve signal integrity on high-speed interfaces up to 480 Mbps.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Working Peak Reverse Voltage | 5.0 V - Matches standard 5 V USB and DVI power rail referencing without overvoltage risk during normal operation. |
| Breakdown Voltage | 6.0 V min @ IT = 1 mA - Ensures reliable turn-on margin above VRWM for robust ESD triggering. |
| Clamping Voltage | 12.5 V @ IPP = 5 A - Limits transient voltage seen by protected ICs to safe levels during 8 kV contact ESD events. |
| Junction Capacitance (I/O–GND) | 3.0–5.0 pF @ VR = 0 V, 1 MHz - Minimizes signal attenuation and timing skew on USB 2.0 differential pairs. |
| Peak Pulse Current | 25 A @ 8 × 20 µs waveform - Withstands multiple high-energy transients per IEC 61000-4-4 (EFT) and lightning surge conditions. |
| ESD Rating | ±20 kV contact / ±20 kV air per IEC 61000-4-2 Level 4 - Exceeds industrial and automotive immunity requirements. |
| Operating Junction Temp | −40 °C to +125 °C - Validated for under-hood automotive and industrial edge computing environments. |
Pinout & Package
TSOP-6 package (Case 318G), dimensions 3.00 × 1.50 × 0.90 mm, 0.95 mm pitch, Pb-free and RoHS compliant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | I/O 1 | First protected data line - connected to USB D+, DVI TMDS+, or display pixel clock. |
| 2 | VN (Ground Reference) | Dedicated low-inductance ground connection - must tie directly to PCB ground plane to minimize clamping overshoot. |
| 3 | N/C | No internal connection - left floating; no routing or termination required. |
| 4 | N/C | No internal connection - left floating; avoids unintended coupling paths. |
| 5 | VP (VCC Reference) | Positive supply reference input - connects to 5 V rail to bias steering diodes and reduce capacitance. |
| 6 | I/O 2 | Second protected data line - paired with Pin 1 for differential signaling (e.g., USB D−, DVI TMDS−). |
Key Features
| Feature | Design Value |
|---|---|
| AEC-Q101 Qualified | Validated for automotive applications including infotainment and ADAS display interfaces with full PPAP documentation support. |
| Low Clamping Voltage | 12.5 V at 5 A enables protection of 3.3 V/5 V logic without requiring additional TVS stages or voltage translators. |
| Ultra-Low Capacitance | 1.5–3.0 pF inter-I/O capacitance preserves signal rise/fall times and eye diagram integrity on 480 Mbps USB 2.0 links. |
| Integrated Dual-Line Protection | Single TSOP-6 package replaces two discrete diodes plus external biasing components, reducing BOM count and layout area by >40%. |
| IEC 61000-4-2/4-4 Compliant | Passes Level 4 ESD (±20 kV contact) and 40 A EFT bursts without degradation - eliminates need for system-level retesting after component change. |
Applications
| USB 2.0 Port Protection | DVI Interface Protection |
|---|---|
|
Use Scenario: Protecting upstream/downstream USB 2.0 ports on laptops, docking stations, and embedded hosts from user-hand ESD events. IC Role / Device Role / Timing Role: ESD transient shunt placed directly at connector, clamping D+ and D− lines to VBUS and chassis ground before reaching USB controller PHY. Use Value: Prevents latch-up and gate oxide damage in USB transceivers while maintaining <100 ps signal delay and <0.1 dB insertion loss at 240 MHz. |
Use Scenario: Shielding DVI-D transmitter outputs on graphics cards and monitor inputs from ESD during cable hot-plug operations. IC Role / Device Role / Timing Role: Low-capacitance steering array referenced to 3.3 V or 5 V rails, suppressing transients on TMDS clock and data channels. Use Value: Maintains HDMI/DVI compliance for 165 MHz pixel clocks with <0.5 UI jitter increase and no visible video artifacts. |
| Flat Panel Display Interface | Automotive Infotainment Link |
|
Use Scenario: Securing LVDS or RSDS video data lanes between GPU and LCD panel in commercial displays and kiosks. IC Role / Device Role / Timing Role: Dual-channel ESD clamp with independent I/O pins, referenced to local ground and VCC to avoid ground bounce coupling. Use Value: Enables 1080p60 video transmission over 30 cm flex cables without added equalization or re-timing. |
Use Scenario: Hardening MIPI D-PHY or FPD-Link III video/data lines in automotive head units and digital instrument clusters. IC Role / Device Role / Timing Role: AEC-Q101-qualified transient suppressor placed at connector entry point, referenced to vehicle battery (5 V) and chassis ground. Use Value: Survives repeated ±15 kV ESD exposure per ISO 10605 while meeting CISPR 25 Class 5 radiated emissions limits. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar ESD protection applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPD2E001DRYR | Lower capacitance (0.9 pF I/O–GND), but lower peak pulse current (12 A) and no AEC-Q101 qualification. | Better suited for ultra-high-speed USB 3.0 Gen1 (5 Gbps) where capacitance dominates; not recommended for automotive use. | Select TPD2E001DRYR only when signal bandwidth exceeds 2 GHz and automotive qualification is unnecessary. |
| ESD5Z5.0T1G | Single-line, SOD-523 package; identical VRWM (5 V) and clamping (12.5 V @ 5 A), but lacks dual-line integration and VCC reference pin. | Requires two devices + external bias network for dual-line protection - increases PCB area and parasitic inductance. | Choose ESD5Z5.0T1G only when board space allows discrete placement and cost sensitivity outweighs layout simplicity. |
Compared with TPD2E001DRYR and ESD5Z5.0T1G, the SZNUP2201MR6T1G uniquely delivers AEC-Q101 compliance, integrated dual-line topology with dedicated VCC reference, and balanced 3–5 pF capacitance-making it the optimal choice for space-constrained, automotive-grade USB/DVI protection where reliability and layout efficiency are prioritized.
Availability
SZNUP2201MR6T1G is available at Aetrix Electronics and suitable for USB 2.0 port hardening, DVI interface shielding, and automotive infotainment video link protection requiring stable component supply across production lifecycles.
Supply support for SZNUP2201MR6T1G includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
onsemi (formerly ON Semiconductor) is a global semiconductor supplier specializing in energy-efficient silicon and SiC solutions for automotive, industrial, cloud, and IoT applications.
The NUP/SZNUP series is engineered specifically for high-reliability transient suppression in high-speed digital interfaces, combining low capacitance, precise clamping, and automotive-grade qualification in compact surface-mount packages.
FAQ
What is the maximum operating temperature range for the SZNUP2201MR6T1G?
The SZNUP2201MR6T1G is rated for an operating junction temperature range of −40 °C to +125 °C. This specification is validated per AEC-Q101 stress testing and supports deployment in under-hood automotive modules, industrial HMIs, and outdoor display enclosures where ambient temperatures exceed 85 °C. The SZNUP2201MR6T1G maintains full ESD clamping performance across this entire range without derating.
Does the SZNUP2201MR6T1G require external biasing components for basic USB 2.0 protection?
No, the SZNUP2201MR6T1G does not require external biasing components for standard USB 2.0 protection. Its integrated VP (pin 5) connects directly to the 5 V VBUS rail, automatically biasing the internal steering diodes to achieve optimal low capacitance (1.5–3.0 pF) and fast clamping response. The SZNUP2201MR6T1G functions correctly with only pins 1 (I/O1), 2 (VN), 5 (VP), and 6 (I/O2) connected - no resistors or capacitors needed.
How does the SZNUP2201MR6T1G differ from the standard NUP2201MR6T1G?
The SZNUP2201MR6T1G is the automotive-grade variant of the NUP2201MR6T1G, distinguished by the "SZ" prefix indicating AEC-Q101 qualification, PPAP capability, and enhanced process controls for automotive applications. Both share identical electrical specs, pinout, and package, but the SZNUP2201MR6T1G undergoes additional stress testing (including temperature cycling, HTRB, and ESD robustness) and receives certified lot traceability - making it mandatory for Tier 1 automotive designs where the standard NUP2201MR6T1G is not accepted.
Can the SZNUP2201MR6T1G protect both differential and single-ended signals?
Yes, the SZNUP2201MR6T1G protects both differential and single-ended signals. Its dual I/O pins (1 and 6) can be assigned to a differential pair (e.g., USB D+/D−) referenced to common ground (pin 2) and VCC (pin 5), or to two independent single-ended lines (e.g., HDMI CEC and HPD). The SZNUP2201MR6T1G's symmetrical clamping architecture ensures matched response time (<1 ns) and voltage threshold across both channels, preserving signal integrity in either configuration.
What is the recommended PCB layout practice for minimizing clamping overshoot with the SZNUP2201MR6T1G?
To minimize clamping overshoot, route the SZNUP2201MR6T1G within 3 mm of the protected connector, connect pin 2 (VN) to a solid ground plane using ≥2 thermal vias, keep I/O traces short and impedance-controlled (50 Ω), and avoid stubs or right-angle bends. The SZNUP2201MR6T1G's performance degrades significantly if VN trace inductance exceeds 1 nH - verified in onsemi Application Note AND8307/D. These practices ensure the SZNUP2201MR6T1G achieves its specified 12.5 V clamping voltage under real-world ESD conditions.
SZNUP2201MR6T1G Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Package/Case:
- SOT-23-6 Thin, TSOT-23-6
- Series:
- -
- Packaging:
- Bulk
- Product Status:
- Discontinued at Digi-Key
- Type:
- Steering (Rail to Rail)
- Unidirectional Channels:
- 2
- Bidirectional Channels:
- -
- Voltage - Reverse Standoff (Typ):
- 5V (Max)
- Voltage - Breakdown (Min):
- 6V
- Voltage - Clamping (Max) @ Ipp:
- 20V
- Current - Peak Pulse (10/1000µs):
- 25A (8/20µs)
- Power - Peak Pulse:
- 500W
- Power Line Protection:
- Yes
- Applications:
- DVI, Telecom, USB
- Capacitance @ Frequency:
- 3pF @ 1MHz
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- Automotive
- Qualification:
- AEC-Q101
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 6-TSOP
SZNUP2201MR6T1G FAQ
1.How can I place an order for SZNUP2201MR6T1G through Aetrix?
Please submit a Request for Quotation (RFQ) for SZNUP2201MR6T1G on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SZNUP2201MR6T1G reliable?
The price and inventory of SZNUP2201MR6T1G are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SZNUP2201MR6T1G is usually 5 days.
3.What payment methods are accepted for SZNUP2201MR6T1G?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SZNUP2201MR6T1G transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SZNUP2201MR6T1G?
SZNUP2201MR6T1G orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SZNUP2201MR6T1G order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SZNUP2201MR6T1G?
For technical support, including SZNUP2201MR6T1G datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SZNUP2201MR6T1G requirements.
6.How does Aetrix verify that SZNUP2201MR6T1G is sourced from the original manufacturer or authorized distributors?
All SZNUP2201MR6T1G products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SZNUP2201MR6T1G meets industry standards.
7.What is the process for return or replacement of SZNUP2201MR6T1G?
All SZNUP2201MR6T1G units undergo pre-shipment inspection (PSI). If there is an issue with SZNUP2201MR6T1G, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SZNUP2201MR6T1G part is unused and in its original packaging.
Return procedure for SZNUP2201MR6T1G:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SZNUP2201MR6T1G Tags

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ESD9B5.0ST5G
onsemi

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DESD3V3E1BL-7B
Diodes Incorporated

-
ESD5Z3.3T1G
onsemi

-
D5V0H1B2LP-7B
Diodes Incorporated

-
D5V0P1B2LP-7B
Diodes Incorporated

-
DESD5V0U1BA-7
Diodes Incorporated

-
ESD5Z5.0T1G
onsemi

-
DESD5V0U1BB-7
Diodes Incorporated

-
D12V0L1B2LP-7B
Diodes Incorporated

-
PESD2V0Y1BSFYL
Nexperia USA Inc.

-
DF2S5M4CT,L3F
Toshiba Semiconductor and Storage

-
D5V0L1B2WS-7
Diodes Incorporated
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