Taiwan Semiconductor Corporation TESD5V0L1UC RJG
- Part No.:
- TESD5V0L1UC RJG
- Manufacturer:
- Taiwan Semiconductor Corporation
- Category:
- TVS Diodes
- Package:
- SOD-882
- Datasheet:
-
TESD5V0L1UC RJG.pdf
- Description:
- TVS DIODE 5VWM 15VC DFN1006L
- Quantity:
- Payment:

- Shipping:

Inventory:8,666
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Product details
Overview
TESD5V0L1UC RJG from Taiwan Semiconductor is a single-channel unidirectional ESD protection diode in DFN1006L package, rated for 5 V working voltage, 2 pF junction capacitance, 3 A peak pulse current (8/20 µs), and ±15 kV air-gap ESD immunity-designed for high-speed USB 2.0 data line protection.
For engineers reviewing the TESD5V0L1UC RJG datasheet, TESD5V0L1UC RJG pinout, TESD5V0L1UC RJG application, or TESD5V0L1UC RJG equivalent, key selection criteria include clamping voltage at 3 A (15 V), low capacitance for signal integrity, IEC 61000-4-2 compliance, and DFN1006L footprint compatibility with space-constrained portable interfaces.
Technical Context
The TESD5V0L1UC RJG implements a single silicon avalanche diode structure optimized for transient suppression on low-voltage, high-bandwidth signal lines. Its 2 pF capacitance at 0 V bias and 6–9.8 V reverse breakdown range ensure minimal signal distortion while maintaining robust ESD clamping.
It operates within –55 °C to +150 °C junction temperature range and supports solder reflow per J-STD-002, with matte tin-plated terminals and JESD201 Class 1A whisker resistance-enabling reliable deployment in notebooks, touch panels, and industrial display interfaces.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VWM | 5 V - Maximum continuous operating voltage before leakage exceeds 0.1 µA; defines safe DC bias margin for USB 2.0 (3.3 V nominal) and VGA/DVI lines. |
| VC @ IPP = 3 A | 15 V - Clamping voltage under 8/20 µs surge; limits downstream IC stress during ESD events without violating 16 V I/O tolerance of most interface transceivers. |
| Junction Capacitance | 2 pF @ 1 MHz, 0 V - Enables <1% signal attenuation at USB 2.0 full-speed (12 MHz) and high-speed (480 MHz) harmonics; preserves eye diagram integrity. |
| IPP | 3 A - Peak 8/20 µs surge current handling; meets IEC 61000-4-5 Level 2 (1 kV) surge immunity when used with series impedance. |
| ESD Rating | ±15 kV air / ±8 kV contact per IEC 61000-4-2 - Exceeds system-level ESD test requirements for consumer-grade notebooks and touch-enabled displays. |
| VBR @ IR = 1 mA | 6–9.8 V - Confirmed avalanche onset range; ensures stable turn-on above VWM while avoiding false triggering during normal operation. |
Pinout & Package
Package: DFN1006L (1.0 mm × 0.6 mm × 0.35 mm), 2-terminal surface-mount device with marked cathode polarity and matte tin-plated leads compliant with J-STD-002 solderability.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| Anode | Signal line input (protected side) | Connected to high-speed data line (e.g., USB D+); conducts transient current to cathode during overvoltage events. |
| Cathode | Ground reference / return path | Connected to system ground plane; provides low-inductance discharge path for ESD energy; marking "BH" identifies cathode end. |
Key Features
| Feature | Design Value |
|---|---|
| IEC 61000-4-2 ESD immunity | ±15 kV air / ±8 kV contact - Validated performance eliminates need for external spark gaps or multi-stage protection in Class B consumer systems. |
| Low junction capacitance | 2 pF - Enables direct placement on differential pairs without degrading signal rise/fall times or causing bit errors in USB 2.0 high-speed mode. |
| Moisture sensitivity level | Level 1 per J-STD-020 - No bake requirement prior to reflow; simplifies SMT assembly for high-volume notebook and monitor manufacturing. |
| Halogen-free & RoHS | Compliant per IEC 61249-2-21 and EU Directive 2011/65/EU - Meets environmental compliance mandates for global OEM shipments including CE and China RoHS. |
Applications
| USB 2.0 Interface Protection | VGA/DVI Signal Line Protection |
|---|---|
Use Scenario: Protecting USB 2.0 D+/D− differential pair in ultrabooks against user-handling ESD events during cable insertion. IC Role / Device Role / Timing Role: Unidirectional TVS diode placed directly at connector, shunting ESD transients to ground before reaching USB PHY. Use Value: 2 pF capacitance prevents signal integrity loss at 480 Mbps; 15 V clamping ensures no damage to 3.3 V tolerant transceivers. | Use Scenario: Shielding analog RGB and sync lines in embedded display modules from ESD induced by finger contact on metal bezels. IC Role / Device Role / Timing Role: Standalone ESD clamp on each signal line, leveraging low leakage (<0.1 µA at 5 V) to avoid DC offset or brightness drift. Use Value: 5 V standoff voltage matches typical VGA I/O rail; ±15 kV air rating covers worst-case field service exposure. |
| Touch Panel Data Lines | Notebook Internal High-Speed Buses |
Use Scenario: Safeguarding I²C or SPI lines between capacitive touch controller and host MCU in thin-film touch sensors. IC Role / Device Role / Timing Role: Low-capacitance transient suppressor on bidirectional control lines, preserving timing margins for 400 kHz I²C fast-mode operation. Use Value: Sub-1 µA leakage at 3.3 V ensures no pull-up current degradation; DFN1006L footprint fits tight pitch (<0.4 mm) flex circuit routing. | Use Scenario: Protecting internal LVDS or eDP auxiliary channel lines in laptop hinge assemblies subject to repeated mechanical stress and ESD coupling. IC Role / Device Role / Timing Role: Point-of-use ESD protection adjacent to connectors, minimizing trace inductance to achieve sub-1 ns response time. Use Value: 3 A peak current rating handles multiple ESD strikes; -55 °C to +150 °C operating range supports extended thermal cycling in chassis-mounted locations. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar ESD protection applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ESD5Z5.0T1G (ON Semiconductor) | Same DFN1006 package, 5.0 V VWM, but 12 V VC @ 3 A and 0.6 pF capacitance. | Lower clamping voltage improves downstream IC safety margin; lower capacitance better suits >1 Gbps interfaces like USB 3.0 Gen1. | Select when tighter clamping or ultra-low capacitance is prioritized over cost; not drop-in due to different marking and minor layout tuning. |
| SMAJ5.0A (Littelfuse) | DO-214AC package, 5.0 V VWM, 15 V VC @ 3 A, but 300 pF capacitance and 1.5 kW PPPSM. | Higher power handling suits industrial surge environments; unsuitable for high-speed data due to excessive capacitance. | Choose only for low-frequency or power-line ESD where speed is irrelevant; requires PCB redesign due to larger footprint and leaded construction. |
Compared with ESD5Z5.0T1G, TESD5V0L1UC RJG offers higher clamping voltage but broader industry validation in USB 2.0 designs; versus SMAJ5.0A, it delivers 150× lower capacitance critical for signal fidelity-making TESD5V0L1UC RJG optimal for compact, high-speed consumer interfaces.
Availability
TESD5V0L1UC RJG is available at Aetrix Electronics and suitable for USB 2.0 interface protection, touch panel data line safeguarding, and VGA/DVI signal line ESD hardening requiring stable component supply across consumer electronics production cycles.
Supply support for TESD5V0L1UC RJG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Taiwan Semiconductor Corporation (TSC) is a vertically integrated analog and discrete semiconductor manufacturer headquartered in Hsinchu Science Park, Taiwan, serving global automotive, industrial, and computing markets since 1979.
The TESD5V0L1UC RJG belongs to TSC's ESD Protection Diode family, engineered specifically for high-speed digital interface protection-balancing ultra-low capacitance, precise clamping, and JEDEC-compliant reliability in miniature DFN packages.
FAQ
What is the maximum clamping voltage of the TESD5V0L1UC RJG under a 3 A ESD surge?
The TESD5V0L1UC RJG clamps to a maximum of 15 V when subjected to a 3 A peak pulse current with an 8/20 µs waveform, as specified in its absolute maximum ratings table. This value ensures protected ICs with 16 V absolute maximum ratings remain within safe operating limits during IEC 61000-4-2 contact discharge events. The TESD5V0L1UC RJG maintains this performance across its full operating temperature range of –55 °C to +150 °C.
Does the TESD5V0L1UC RJG support USB 2.0 high-speed (480 Mbps) signal integrity?
Yes, the TESD5V0L1UC RJG supports USB 2.0 high-speed operation due to its 2 pF junction capacitance at 0 V bias and low leakage (<0.1 µA at 5 V), which minimizes signal distortion and preserves eye diagram margins. Its DFN1006L footprint allows placement directly at the USB connector with minimal stub length-critical for maintaining impedance continuity. The TESD5V0L1UC RJG has been validated in reference designs for ultrabook USB ports.
What is the moisture sensitivity level (MSL) rating for the TESD5V0L1UC RJG?
The TESD5V0L1UC RJG is rated MSL Level 1 per J-STD-020, meaning it may be stored indefinitely at ≤30 °C/60% RH and requires no baking prior to reflow soldering. This simplifies manufacturing logistics for high-volume SMT lines producing notebooks and monitors. The TESD5V0L1UC RJG's epoxy molding compound also meets UL 94V-0 flammability standards.
Is the TESD5V0L1UC RJG halogen-free and RoHS compliant?
Yes, the TESD5V0L1UC RJG is both RoHS compliant per EU Directive 2011/65/EU and halogen-free per IEC 61249-2-21, verified through material declarations and third-party testing. These certifications enable unrestricted shipment into EU, China, and other regulated markets. The TESD5V0L1UC RJG's compliance documentation is available upon request from Aetrix Electronics.
What marking code appears on the TESD5V0L1UC RJG device body?
The TESD5V0L1UC RJG is marked with "BH" on its top surface, indicating cathode polarity per standard diode orientation conventions. This marking aligns with the DFN1006L package outline and is visible under 20× magnification for automated optical inspection (AOI). The TESD5V0L1UC RJG's marking is laser-etched for durability across reflow and cleaning processes.
TESD5V0L1UC RJG Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Taiwan Semiconductor Corporation
- Package/Case:
- SOD-882
- Series:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Type:
- Zener
- Unidirectional Channels:
- -
- Bidirectional Channels:
- 1
- Voltage - Reverse Standoff (Typ):
- 5V (Max)
- Voltage - Breakdown (Min):
- 6V
- Voltage - Clamping (Max) @ Ipp:
- 15V
- Current - Peak Pulse (10/1000µs):
- 3A (8/20µs)
- Power - Peak Pulse:
- 100W
- Power Line Protection:
- No
- Applications:
- General Purpose
- Capacitance @ Frequency:
- 2pF @ 1MHz
- Operating Temperature:
- -55°C ~ 155°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- DFN1006L
TESD5V0L1UC RJG FAQ
1.How can I place an order for TESD5V0L1UC RJG through Aetrix?
Please submit a Request for Quotation (RFQ) for TESD5V0L1UC RJG on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TESD5V0L1UC RJG reliable?
The price and inventory of TESD5V0L1UC RJG are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TESD5V0L1UC RJG is usually 5 days.
3.What payment methods are accepted for TESD5V0L1UC RJG?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TESD5V0L1UC RJG transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TESD5V0L1UC RJG?
TESD5V0L1UC RJG orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TESD5V0L1UC RJG order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TESD5V0L1UC RJG?
For technical support, including TESD5V0L1UC RJG datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TESD5V0L1UC RJG requirements.
6.How does Aetrix verify that TESD5V0L1UC RJG is sourced from the original manufacturer or authorized distributors?
All TESD5V0L1UC RJG products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TESD5V0L1UC RJG meets industry standards.
7.What is the process for return or replacement of TESD5V0L1UC RJG?
All TESD5V0L1UC RJG units undergo pre-shipment inspection (PSI). If there is an issue with TESD5V0L1UC RJG, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TESD5V0L1UC RJG part is unused and in its original packaging.
Return procedure for TESD5V0L1UC RJG:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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