Texas Instruments TPD1E0B04DPYR
- Part No.:
- TPD1E0B04DPYR
- Manufacturer:
- Texas Instruments
- Category:
- TVS Diodes
- Package:
- 0402 (1006 Metric)
- Datasheet:
-
TPD1E0B04DPYR.pdf
- Description:
- TVS DIODE 3.6VWM 19VC 2X1SON
- Quantity:
- Payment:

- Shipping:

Inventory:15,150
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Product details
Overview
TPD1E0B04DPYR from Texas Instruments is a single-channel bidirectional TVS ESD protection diode in X1SON (DPY) package, rated for ±8kV contact / ±9kV air-gap IEC 61000-4-2 ESD suppression, 0.15–0.18pF max line capacitance, and DC breakdown voltage of ±6.7V (typ), designed for USB Type-C, Thunderbolt 4, and 5GHz WiFi antenna signal-line protection.
For engineers reviewing the TPD1E0B04DPYR datasheet, TPD1E0B04DPYR pinout, TPD1E0B04DPYR application, or TPD1E0B04DPYR equivalent, this page delivers verified electrical parameters, package-specific thermal metrics, real-world insertion loss performance up to 30GHz, clamping behavior under 1A–16A TLP pulses, and validated use cases in high-speed differential pairs and RF front-end paths.
Technical Context
The TPD1E0B04DPYR operates as a passive, bidirectional clamping diode with symmetrical breakdown (±6.7V typ) and ultra-low dynamic resistance (1Ω). Its ESD response triggers within nanoseconds when transient voltages exceed VBRF/VBRR, diverting surge current to ground while maintaining clamping voltage ≤10.1V at 5A TLP.
Designed for signal integrity preservation, it delivers <−0.5dB insertion loss up to 10GHz and −3dB bandwidth >30GHz (DPY package), with capacitance stable across −40°C to +125°C and bias voltages up to ±3.6V - enabling direct placement on 10Gbps+ SuperSpeed lanes and 5.8GHz antenna feeds without impedance discontinuity.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| ESD Rating (IEC 61000-4-2) | ±8kV contact / ±9kV air-gap discharge - meets Level 4 immunity for handheld interface ports |
| Line Capacitance (DPY) | 0.15–0.18pF max at 1MHz - preserves signal integrity on USB4/Thunderbolt 4 differential pairs |
| DC Breakdown Voltage | ±6.7V typical - protects ICs with 3.3V/5V I/O rails while tolerating ±3.6V operating range |
| Clamping Voltage (5A TLP) | 10.1V max (IO-to-GND) - limits stress on downstream PHY transceivers during ESD events |
| Leakage Current | ≤10nA at ±2.5V - avoids DC loading on sensitive RF or high-impedance analog lines |
| Surge Rating (IEC 61000-4-5) | 1.7A (8/20µs) - withstands induced lightning-induced transients on exposed connectors |
| Operating Temperature | −40°C to +125°C - supports industrial and automotive under-hood/edge-compute deployments |
Pinout & Package
X1SON (DPY) 2-pin surface-mount package: 1.00mm × 0.60mm footprint, 0.4mm nominal height, single-row layout optimized for minimal trace inductance in high-frequency routing.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | I/O | ESD-protected signal terminal; connects to protected line (e.g., SSTX1P, CC1, or antenna feed); must be paired with Pin 2 to GND |
| 2 | GND | Low-inductance ground return path for ESD current; requires direct connection to solid ground plane beneath device |
Key Features
| Feature | Design Value |
|---|---|
| Bidirectional clamping | ±6.7V symmetric breakdown enables protection of AC-coupled or floating differential signals without polarity constraints |
| Ultra-low capacitance | 0.15–0.18pF max ensures <0.1dB insertion loss at 10GHz - critical for USB4 Gen 3 (40Gbps) and Thunderbolt 4 compliance |
| Low dynamic resistance | 1Ω typical minimizes VCLAMP rise under high-current ESD strikes, reducing risk of latch-up in downstream ICs |
| RF-optimized layout | Asymmetric pad geometry and short internal bond wires reduce parasitic inductance - validated by 30GHz −3dB bandwidth |
| Industrial temp support | Specified performance over −40°C to +125°C enables use in automotive infotainment, industrial docking, and outdoor AP designs |
Applications
| USB Type-C Interface Protection | Thunderbolt 4 Data Lane Protection |
|---|---|
Use Scenario: Protecting SSTX/SSTX differential pairs on a laptop USB-C port against user-handling ESD. IC Role / Device Role / Timing Role: Passive ESD clamp placed between connector and USB-C controller PHY, shunting transients before they reach silicon. Use Value: Maintains eye diagram integrity at 10Gbps (USB 3.2 Gen 2) with <0.5dB loss at 5GHz - verified via TI's Figure 7-3 eye diagrams. |
Use Scenario: Securing four differential lanes in a Thunderbolt 4 dock supporting 40Gbps bidirectional data + DP Alt Mode. IC Role / Device Role / Timing Role: Per-lane ESD suppressor on each TX/RX pair, leveraging symmetrical clamping to avoid signal inversion or DC offset. Use Value: Enables full 40Gbps throughput with <−0.3dB insertion loss up to 20GHz - confirmed by Figure 5-11 DPY curve. |
| 5GHz WiFi Antenna Feed Protection | High-Speed DisplayPort Line Protection |
Use Scenario: Adding ESD robustness to the antenna feed line of a dual-band WiFi 6E access point operating at 5.17–5.835GHz. IC Role / Device Role / Timing Role: Series-connected TVS on RF path between PA output and antenna switch, grounded at Pin 2. Use Value: Adds <0.02pF parasitic capacitance shift across band - negligible VSWR impact per Figure 7-6 capacitance vs frequency plot. |
Use Scenario: Shielding DisplayPort 2.1 source outputs (UHBR13.5, 80Gbps aggregate) from ESD during cable hot-plug events. IC Role / Device Role / Timing Role: One TPD1E0B04DPYR per differential lane (TX0+/− through TX4+/−), placed adjacent to connector. Use Value: Supports >30GHz bandwidth with <−1dB loss at 13.5GHz - sufficient for UHBR13.5 signaling per Figure 5-11. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar ESD protection applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPD1E0B04DPLR | Same die, DPL (X2SON, 0.6×0.3mm) package - 0.13–0.15pF max capacitance, higher thermal resistance (RθJA = 582°C/W) | Better for space-constrained layouts; lower capacitance suits >40Gbps links but less robust thermal dissipation | Select DPL for ultra-dense PCBs where 0.13pF margin is critical; choose DPY for better power handling and manufacturability. |
| SMA6J5.0A | Unidirectional, DO-214AC package, 5V VBR, 65pF min capacitance - 400× higher capacitance than TPD1E0B04DPYR | Only suitable for low-speed DC/low-frequency lines (e.g., VBUS, CC), not high-speed data lanes | Use only for non-signal-line protection; incompatible with USB4/Thunderbolt due to excessive RF loading. |
Compared with TPD1E0B04DPLR, TPD1E0B04DPYR trades 0.02pF higher capacitance for 30% lower RθJA and improved assembly yield; versus SMA6J5.0A, it provides 99.8% lower capacitance and true bidirectional operation - making it the sole viable option for >10Gbps differential interfaces.
Availability
TPD1E0B04DPYR is available at Aetrix Electronics and suitable for USB Type-C docking stations, Thunderbolt 4 host controllers, and 5GHz WiFi antenna modules requiring stable component supply, long-term lifecycle assurance, and RoHS-compliant sourcing.
Supply support for TPD1E0B04DPYR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor company delivering analog and embedded processing solutions, with leadership in precision analog, high-speed interface, and power management technologies.
The TPD1E0B04 series belongs to TI's ESD protection portfolio, engineered specifically for preserving signal integrity on next-generation high-speed interconnects including USB4, Thunderbolt, and mmWave RF paths.
FAQ
What is the maximum operating frequency supported by TPD1E0B04DPYR?
TPD1E0B04DPYR maintains <−0.5dB insertion loss up to 10GHz and exhibits −3dB bandwidth exceeding 30GHz, as confirmed by TI's Figure 5-11. This enables reliable use in USB4 Gen 3 (40Gbps), Thunderbolt 4 (40Gbps), and 5GHz WiFi antenna paths - all of which operate well within its RF performance envelope. The DPY package's 0.15–0.18pF capacitance ensures minimal phase distortion.
Does TPD1E0B04DPYR require external bias or power connections?
No, TPD1E0B04DPYR is a fully passive TVS diode array with no power pins or control inputs. It operates solely via avalanche breakdown triggered by overvoltage events. Pin 1 connects to the protected signal line (e.g., SSTX1P), and Pin 2 must be tied directly to a low-inductance ground plane - no decoupling capacitors or voltage rails are needed.
How does TPD1E0B04DPYR compare to TPD1E0B04DPLR in thermal performance?
TPD1E0B04DPYR has a junction-to-board thermal resistance (RθJB) of 162.5°C/W versus 394.4°C/W for TPD1E0B04DPLR, per TI's SLVSDG9C datasheet Section 5.5. This 59% improvement allows DPY to dissipate surge energy more effectively in thermally constrained layouts, especially during repeated EFT bursts or multi-pulse ESD events.
Can TPD1E0B04DPYR protect both USB Type-C CC and SBU lines?
Yes - TPD1E0B04DPYR supports ±3.6V operating voltage (Section 5.4) and ±6.7V DC breakdown, covering the full CC/SBU signaling range (0–5V). Its 10nA max leakage avoids disrupting CC logic detection, and its 0.15–0.18pF capacitance introduces negligible delay on 480MHz SBU lines, as validated in TI's USB Type-C design example (Section 7.2.1.2).
Is TPD1E0B04DPYR compatible with lead-free reflow profiles?
Yes, TPD1E0B04DPYR carries MSL Level-1 rating with peak reflow tolerance up to 260°C (unlimited floor life), and uses NiPdAu/NiPdAuAg lead finish per TI's Packaging Information table. It complies with IPC/JEDEC J-STD-020D.3 and is qualified for standard Pb-free soldering processes without derating.
TPD1E0B04DPYR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Package/Case:
- 0402 (1006 Metric)
- Series:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Type:
- Zener
- Unidirectional Channels:
- -
- Bidirectional Channels:
- 1
- Voltage - Reverse Standoff (Typ):
- 3.6V
- Voltage - Breakdown (Min):
- 6.7V (Typ)
- Voltage - Clamping (Max) @ Ipp:
- 19V
- Current - Peak Pulse (10/1000µs):
- 1.7A (8/20µs)
- Power - Peak Pulse:
- 15W
- Power Line Protection:
- No
- Applications:
- General Purpose
- Capacitance @ Frequency:
- 0.15pF @ 1MHz
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 2-X1SON (1x.60)
TPD1E0B04DPYR FAQ
1.How can I place an order for TPD1E0B04DPYR through Aetrix?
Please submit a Request for Quotation (RFQ) for TPD1E0B04DPYR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TPD1E0B04DPYR reliable?
The price and inventory of TPD1E0B04DPYR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPD1E0B04DPYR is usually 5 days.
3.What payment methods are accepted for TPD1E0B04DPYR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TPD1E0B04DPYR transactions.
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4.How is shipping managed for TPD1E0B04DPYR?
TPD1E0B04DPYR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TPD1E0B04DPYR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TPD1E0B04DPYR?
For technical support, including TPD1E0B04DPYR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPD1E0B04DPYR requirements.
6.How does Aetrix verify that TPD1E0B04DPYR is sourced from the original manufacturer or authorized distributors?
All TPD1E0B04DPYR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPD1E0B04DPYR meets industry standards.
7.What is the process for return or replacement of TPD1E0B04DPYR?
All TPD1E0B04DPYR units undergo pre-shipment inspection (PSI). If there is an issue with TPD1E0B04DPYR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TPD1E0B04DPYR part is unused and in its original packaging.
Return procedure for TPD1E0B04DPYR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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