Texas Instruments TPD4S009DCKRG4
- Part No.:
- TPD4S009DCKRG4
- Manufacturer:
- Texas Instruments
- Category:
- TVS Diodes
- Package:
- 6-TSSOP, SC-88, SOT-363
- Datasheet:
-
TPD4S009DCKRG4.pdf
- Description:
- TVS DIODE 5.5VWM SC70-6
- Quantity:
- Payment:

- Shipping:

Inventory:9,253
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Product details
Overview
TPD4S009DCKRG4 from Texas Instruments is a 4-channel TVS diode array for IEC 61000-4-2 Level 4 ESD protection of high-speed differential interfaces, featuring ±8-kV contact discharge rating, 0.8-pF typical I/O capacitance, 10-nA typical leakage current at 3.3 V, and support for >4 GHz bandwidth - deployed in USB 2.0, HDMI 1.4, and LVDS port protection.
For engineers reviewing the TPD4S009DCKRG4 datasheet, TPD4S009DCKRG4 pinout, TPD4S009DCKRG4 application, or TPD4S009DCKRG4 equivalent, this page delivers verified package mapping (SC70-6), confirmed pin functions (D1+/D1−/D2+/D2−/GND/VCC), differential pair matching data (0.05-pF line-line), Ioff capability, and real-world layout guidance for HDMI/USB signal integrity preservation.
Technical Context
The TPD4S009DCKRG4 implements a monolithic silicon TVS structure with bidirectional clamping diodes per channel, triggered by voltage excursions beyond ±9 V breakdown (VBR) or below −0.6 V forward conduction. Its internal architecture includes a dedicated VCC pin with blocking diode enabling Ioff functionality - allowing live-signal operation on D+/D− when VCC = 0 V - critical for hot-plug HDMI compliance.
It operates passively without power but leverages VCC biasing to stabilize internal node potentials during system startup; this does not affect ESD performance. The device sustains 2.5-A (8/20 µs) surge events per IEC 61000-4-5 while maintaining <1.1-Ω dynamic resistance (RDYN) and clamping voltage (VCLAMP) low enough to protect downstream 3.3-V/5-V interface ICs.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| ESD Protection | ±8-kV contact / ±9-kV air per IEC 61000-4-2 Level 4 - ensures system-level robustness against human-hand ESD events at connectors. |
| I/O Capacitance | 0.8 pF (typical) per pin to GND - preserves signal integrity up to 3.4 Gbps (HDMI 1.4) with minimal insertion loss. |
| Line-to-Line Matching | 0.05-pF capacitance mismatch between D1+/D1− and D2+/D2− - minimizes intra-pair skew critical for TMDS timing budgets. |
| Breakdown Voltage (VBR) | 9 V (min) at 1 mA - defines precise clamping threshold to avoid false triggering during normal 3.3-V/5-V signal swings. |
| Dynamic Resistance (RDYN) | 1.1 Ω (typical) - enables low-voltage clamping (<12 V @ 2.5 A), protecting sensitive PHY receivers from overstress. |
| Leakage Current | 10 nA (typical) at 3.3 V IO / 5 V VCC - prevents DC loading on high-impedance data lines and maintains receiver sensitivity. |
| Operating Temperature | −40°C to +85°C - supports industrial-grade deployment in set-top boxes, laptops, and point-of-sale terminals. |
Pinout & Package
TPD4S009DCKRG4 uses the SC70-6 (DCK) package: 2.00 mm × 1.25 mm body, 0.65-mm pitch, 1.1-mm max height, lead-free NiPdAu finish, MSL Level-1.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| D1+ | ESD clamp input (Channel 1, positive) | Protects high-speed differential signal line (e.g., HDMI TMDS D1+ or USB D+) with matched capacitance to D1−. |
| D1− | ESD clamp input (Channel 1, negative) | Paired with D1+; 0.05-pF inter-pin capacitance match ensures minimal differential skew under ESD transients. |
| GND | Reference ground terminal | Low-inductance return path for ESD current; must connect directly to solid ground plane near connector. |
| D2+ | ESD clamp input (Channel 2, positive) | Second protected differential pair (e.g., HDMI D2+ or USB ID); electrically identical to D1+ with same specs. |
| D2− | ESD clamp input (Channel 2, negative) | Paired with D2+; maintains same 0.05-pF matching as D1+/D1− for consistent dual-lane timing behavior. |
| VCC | Optional supply bias pin | Enables Ioff mode: allows live signals on D+/D− when VCC = 0 V; no effect on ESD clamping if left unconnected. |
Key Features
| Feature | Design Value |
|---|---|
| Ioff functionality | VCC-biased internal blocking diode permits safe hot-plug operation on HDMI/USB lines even when host is powered off. |
| Differential pair capacitance matching | 0.05-pF line-to-line mismatch ensures <0.1-ps intra-pair skew - essential for HDMI 1.4 eye diagram compliance. |
| Ultra-low I/O capacitance | 0.8 pF (typical) per pin enables >4 GHz bandwidth - supports 3.4-Gbps data rates without measurable signal degradation. |
| IEC 61000-4-5 surge immunity | 2.5-A (8/20 µs) surge withstand - protects against lightning-induced surges and cable discharge events in field-deployed equipment. |
| Industrial temperature range | −40°C to +85°C operation - validated across full range for reliability in consumer electronics and embedded industrial systems. |
Applications
| HDMI 1.4 Port Protection | USB 2.0 Interface Protection |
|---|---|
Use Scenario: Protecting TMDS differential pairs (D0+/D0−, D1+/D1−, D2+/D2−, CLK+/CLK−) on HDMI source/sink connectors against user-hand ESD. IC Role / Device Role / Timing Role: Passive TVS clamp placed between connector and HDMI PHY, providing sub-10-ns response to ±8-kV discharges while preserving 1.7-GHz fundamental frequency. Use Value: Maintains HDMI eye opening >80% at 3.4 Gbps due to 0.8-pF capacitance and 0.05-pF pair matching - avoids link training failures or pixel corruption. |
Use Scenario: Shielding upstream/downstream D+/D− lines on USB 2.0 Type-A/B/Micro-B ports from ESD during cable insertion/removal. IC Role / Device Role / Timing Role: Bidirectional ESD suppressor with Ioff support, enabling D+/D− to remain active during host suspend states (VCC = 0 V). Use Value: Prevents USB enumeration failure after repeated ±8-kV contact strikes; leakage <10 nA avoids false disconnect detection by USB transceivers. |
| Laptop Docking Station I/O | Set-Top Box Front-Panel Interfaces |
Use Scenario: Securing multiple high-speed interfaces (HDMI, USB, LVDS) on compact docking station PCBs where space and signal fidelity are constrained. IC Role / Device Role / Timing Role: Dual-channel flow-through protector (D1+/D1− + D2+/D2−) in SC70-6 footprint, enabling straight routing with <2-mm trace length from connector to device. Use Value: Eliminates need for vias or stubs - reduces impedance discontinuities and crosstalk between adjacent differential lanes in dense layouts. |
Use Scenario: Hardening HDMI and USB ports on consumer STB front panels exposed to frequent user interaction and environmental ESD. IC Role / Device Role / Timing Role: Industrial-grade transient suppressor operating continuously from −40°C to +85°C, surviving 1000+ ESD events per IEC test cycles. Use Value: Extends field service life by preventing PHY latch-up or gate oxide damage - reduces warranty returns linked to port failure. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar ESD protection applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPD4S010DQAR | 10-pin USON package; no VCC pin; identical 0.8-pF capacitance and ±8-kV ESD rating but lacks Ioff functionality. | Preferred for space-constrained layouts requiring flow-through routing on 10-pin footprints; unsuitable for hot-plug HDMI where VCC = 0 V is required. | Select when Ioff is unnecessary and board layout favors USON-10's symmetric pinout for differential pair symmetry. |
| TPD4E05U06DQAR | Lower 5.5-V standoff (VRWM), 0.5-pF capacitance, higher 12-V clamping voltage; P2P compatible with TPD4S010DQAR but not TPD4S009DCKRG4. | Better suited for 3.3-V-only systems needing tighter clamping margin; incompatible with TPD4S009DCKRG4's SC70-6 footprint and VCC pin. | Choose only if reducing capacitance to 0.5 pF is critical and system voltage never exceeds 5.5 V - requires PCB redesign. |
Compared with TPD4S010DQAR, TPD4S009DCKRG4 adds Ioff support and fits smaller SC70-6 area but requires VCC routing; versus TPD4E05U06DQAR, it offers higher VRWM and proven HDMI 1.4 compatibility at the cost of slightly higher capacitance.
Availability
TPD4S009DCKRG4 is available at Aetrix Electronics and suitable for HDMI 1.4 port protection, USB 2.0 interface hardening, and industrial set-top box designs requiring stable component supply, long-term lifecycle assurance, and RoHS-compliant sourcing.
Supply support for TPD4S009DCKRG4 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor company specializing in analog, embedded processing, and high-reliability components, with decades of leadership in ESD protection and interface solutions.
TPD4S009DCKRG4 belongs to TI's transient voltage suppression portfolio designed specifically for high-speed differential data interfaces - balancing ultra-low capacitance, precise clamping, and industrial environmental resilience.
FAQ
What is the primary function of the VCC pin on TPD4S009DCKRG4?
The VCC pin on TPD4S009DCKRG4 enables the Ioff feature: it biases an internal blocking diode so the device can safely handle live signals on D1+/D1− and D2+/D2− even when VCC = 0 V. This is essential for HDMI hot-plug compliance. TPD4S009DCKRG4 remains fully functional without VCC connection, and ESD performance is unaffected whether VCC is tied to 3.3 V, 5 V, or left floating.
Does TPD4S009DCKRG4 support HDMI 1.4 data rates?
Yes, TPD4S009DCKRG4 supports HDMI 1.4's 3.4-Gbps data rate via its >4 GHz (−3 dB) bandwidth, enabled by 0.8-pF typical I/O capacitance and 0.05-pF differential pair matching. Eye diagram measurements confirm <10% degradation at 1.7 GHz fundamental frequency, meeting HDMI 1.4 electrical compliance requirements when placed within 5 mm of the connector.
How does TPD4S009DCKRG4 differ from TPD4S010DQAR?
TPD4S009DCKRG4 uses SC70-6 packaging with a VCC pin enabling Ioff mode; TPD4S010DQAR uses 10-pin USON packaging without VCC. Both offer ±8-kV ESD protection and 0.8-pF capacitance, but only TPD4S009DCKRG4 supports live-signal operation during host power-off - making it mandatory for HDMI-compliant designs where D+/D− must remain active before VCC ramps.
What is the maximum surge current TPD4S009DCKRG4 can handle?
TPD4S009DCKRG4 withstands 2.5 A peak pulse current (8/20 µs waveform) per IEC 61000-4-5, dissipating up to 25 W transient power. This surge rating applies independently to each I/O pin (D1+, D1−, D2+, D2−) referenced to GND, with clamping voltage held below 12 V at 2.5 A - sufficient to protect common HDMI and USB PHY ICs.
Is TPD4S009DCKRG4 compatible with automated SMT assembly?
Yes, TPD4S009DCKRG4 is qualified for standard SMT reflow per JEDEC J-STD-020: SC70-6 package has MSL Level-1 rating (unlimited floor life at ≤30°C/60% RH), lead-free NiPdAu finish, and 260°C peak reflow tolerance. Recommended stencil aperture is 0.5 mm × 0.5 mm with 0.125-mm thickness for optimal solder paste release and coplanarity control.
TPD4S009DCKRG4 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Package/Case:
- 6-TSSOP, SC-88, SOT-363
- Series:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Discontinued at Digi-Key
- Type:
- Steering (Rail to Rail)
- Unidirectional Channels:
- 4
- Bidirectional Channels:
- -
- Voltage - Reverse Standoff (Typ):
- 5.5V (Max)
- Voltage - Breakdown (Min):
- 9V
- Voltage - Clamping (Max) @ Ipp:
- -
- Current - Peak Pulse (10/1000µs):
- -
- Power - Peak Pulse:
- 25W
- Power Line Protection:
- Yes
- Applications:
- Ethernet, HDMI
- Capacitance @ Frequency:
- -
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- SC-70-6
TPD4S009DCKRG4 FAQ
1.How can I place an order for TPD4S009DCKRG4 through Aetrix?
Please submit a Request for Quotation (RFQ) for TPD4S009DCKRG4 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TPD4S009DCKRG4 reliable?
The price and inventory of TPD4S009DCKRG4 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPD4S009DCKRG4 is usually 5 days.
3.What payment methods are accepted for TPD4S009DCKRG4?
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4.How is shipping managed for TPD4S009DCKRG4?
TPD4S009DCKRG4 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TPD4S009DCKRG4 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TPD4S009DCKRG4?
For technical support, including TPD4S009DCKRG4 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPD4S009DCKRG4 requirements.
6.How does Aetrix verify that TPD4S009DCKRG4 is sourced from the original manufacturer or authorized distributors?
All TPD4S009DCKRG4 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPD4S009DCKRG4 meets industry standards.
7.What is the process for return or replacement of TPD4S009DCKRG4?
All TPD4S009DCKRG4 units undergo pre-shipment inspection (PSI). If there is an issue with TPD4S009DCKRG4, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TPD4S009DCKRG4 part is unused and in its original packaging.
Return procedure for TPD4S009DCKRG4:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
TPD4S009DCKRG4 Tags

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onsemi

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DESD3V3E1BL-7B
Diodes Incorporated

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Diodes Incorporated

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Diodes Incorporated

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Diodes Incorporated

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onsemi

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Diodes Incorporated

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Diodes Incorporated

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Nexperia USA Inc.

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Toshiba Semiconductor and Storage

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Diodes Incorporated
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