onsemi TVS8814MUTAG
- Part No.:
- TVS8814MUTAG
- Manufacturer:
- onsemi
- Category:
- TVS Diodes
- Package:
- -
- Datasheet:
-
TVS8814MUTAG.pdf
- Description:
- 4 CHANNEL TVS ARRAY
- Quantity:
- Payment:

- Shipping:

Inventory:252,000
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
TVS8814MUTAG from onsemi is a unidirectional 4-channel transient voltage suppressor designed for high-speed Ethernet signal line protection. It delivers 3.0 V working peak reverse voltage, ≤2.0 pF I/O-to-I/O capacitance, and clamps to 15 V at 35 A (8/20 µs), enabling robust ESD (±30 kV contact) and lightning surge (35 A) protection for 10/100/GbE PHY interfaces without degrading signal integrity.
For engineers reviewing the TVS8814MUTAG datasheet, pinout, applications, or equivalent options, key selection criteria include low inter-pin capacitance (≤2.0 pF), flow-thru routing compatibility with differential pair layout, common-GND architecture, and UDFN8 package footprint for impedance-controlled PCB design in MagJack-integrated Ethernet ports.
Technical Context
The TVS8814MUTAG integrates four independent unidirectional TVS diodes in a single UDFN8 package with shared GND terminals (Pins 1, 4, 5, 8). Its flow-thru pin arrangement-input/output pins aligned linearly across the package-enables symmetric trace routing for differential pairs, minimizing skew and maintaining 100 Ω differential impedance.
It operates within −55 °C to +125 °C junction temperature range and meets IEC 61000−4−2 (±30 kV contact), IEC 61000−4−5 (35 A, 8/20 µs), and UL 94 V−0 flammability standards. The device uses silicon avalanche technology with dynamic resistance <0.5 Ω to achieve fast response (<1 ns) and low clamping voltage under surge conditions.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Working Peak Voltage | 3.0 V - Matches typical 3.3 V Ethernet PHY supply rails while providing margin above DC operating voltage. |
| Max I/O-to-I/O Capacitance | 2.0 pF - Preserves signal integrity up to 1.25 Gbps in 100BASE-TX and 1000BASE-T applications. |
| Clamping Voltage @ 35 A | 15 V - Limits transient overvoltage below absolute maximum rating of Ethernet transceivers (typically 16–18 V). |
| ESD Protection Level | ±30 kV contact - Exceeds IEC 61000−4−2 Level 4 requirement (±8 kV) for industrial and enterprise equipment. |
| Surge Current Rating | 35 A (8/20 µs) - Withstands multi-pulse lightning-induced surges per IEC 61000−4−5 for outdoor or PoE-enabled ports. |
| Package | UDFN8 (2.2 × 2.0 mm, 0.575 mm pitch) - Enables compact, low-inductance layout adjacent to RJ-45 connector or MagJack. |
Pinout & Package
TVS8814MUTAG uses an 8-pin UDFN package (Case 506CV) with exposed thermal pad. Pinout follows flow-thru routing: Pins 2/3/6/7 are I/O channels; Pins 1/4/5/8 are common GND connections. Minimum one GND connection required; multiple GND pins reduce ground inductance and improve clamping consistency.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| Pin 1, 4, 5, 8 | Common GND | Shared cathode reference for all four TVS channels; low-inductance grounding path critical for effective clamping. |
| Pin 2 | I/O Channel 1 | Protected line for TX+ or RX+ differential pair; bidirectional signal path with low capacitance. |
| Pin 3 | I/O Channel 2 | Protected line for TX− or RX− differential pair; matched to Pin 2 for balanced layout. |
| Pin 6 | I/O Channel 3 | Second differential pair leg (e.g., auxiliary 100BASE-TX or secondary GbE lane). |
| Pin 7 | I/O Channel 4 | Complementary leg to Pin 6; enables full 4-line protection in compact footprint. |
Key Features
| Feature | Design Value |
|---|---|
| Flow-thru routing architecture | Enables straight-through PCB trace routing for differential pairs, eliminating vias and stubs that degrade impedance matching. |
| ≤2.0 pF I/O-to-I/O capacitance | Minimizes insertion loss and crosstalk in 100 MHz–1 GHz Ethernet bands, preserving eye diagram margins. |
| ±30 kV IEC 61000−4−2 ESD rating | Eliminates need for external ESD staging components in front-end protection schemes for MagJack modules. |
| UL 94 V−0 flammability rating | Meets safety compliance for enclosed networking equipment without additional flame-retardant housing. |
| Pb-free UDFN8 package | Supports RoHS-compliant reflow assembly and thermal cycling reliability in industrial temperature environments. |
Applications
| 10/100BASE-TX Ethernet Port | Gigabit Ethernet (1000BASE-T) Interface |
|---|---|
Use Scenario: Protection of twisted-pair differential signals between RJ-45 connector and PHY IC in desktop switches or IP cameras. IC Role / Device Role / Timing Role: Unidirectional TVS array clamping transient energy before it reaches the PHY's ESD-sensitive input stage. Use Value: Maintains <2.0 pF inter-pin capacitance to avoid signal rise-time degradation and ensures <15 V clamping at 35 A surge current. | Use Scenario: Surge suppression on all four differential pairs in GbE ports with integrated magnetics (MagJacks®). IC Role / Device Role / Timing Role: Front-end transient suppressor placed immediately after the transformer center-tap, sharing common GND with PHY. Use Value: Flow-thru pinout allows matched-length traces across all eight lines, preserving 100 Ω differential impedance and reducing bit error rate. |
| Notebook/Laptop LAN Interface | Industrial Ethernet Controller Module |
Use Scenario: Space-constrained Ethernet PHY protection in thin-client devices where board area is limited. IC Role / Device Role / Timing Role: Single-package solution replacing discrete TVS diodes for each differential pair, reducing BOM count by 75%. Use Value: 2.2 × 2.0 mm UDFN8 footprint saves >60% board area versus SOIC-8 alternatives while delivering identical surge performance. | Use Scenario: Ruggedized Ethernet interface in factory automation controllers exposed to electrical noise and lightning-induced surges. IC Role / Device Role / Timing Role: Primary surge protection layer meeting IEC 61000−4−5 Level 3 (35 A) requirements for industrial environments. Use Value: −55 °C to +125 °C operating range ensures reliability in uncontrolled ambient conditions without derating. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar TVS protection applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SMAJ3.3A | Single-channel SMA package; 3.3 V VRWM; 100 pF I/O-to-GND capacitance; no flow-thru routing. | Requires four discrete devices and complex layout to match differential pair symmetry; unsuitable for GbE. | Select only for cost-sensitive, low-speed (<10 Mbps), non-differential applications where board space is not constrained. |
| SP3052-04UTG | 4-channel SOT-23-6 package; 3.3 V VRWM; 0.6 pF I/O-to-I/O; but uses side-entry routing and lacks common-GND architecture. | Higher layout complexity due to non-linear pinout; requires more vias and longer traces, increasing impedance discontinuity risk. | Prefer when ultra-low capacitance (<0.7 pF) is mandatory and flow-thru routing is not required for signal integrity. |
Compared with SMAJ3.3A and SP3052-04UTG, TVS8814MUTAG uniquely combines 4-channel integration, flow-thru routing, ≤2.0 pF I/O-to-I/O capacitance, and common-GND topology-making it the only option qualified for production-grade 1000BASE-T port protection with minimal PCB impact.
Availability
TVS8814MUTAG is available at Aetrix Electronics and suitable for 10/100BASE-TX Ethernet ports, Gigabit Ethernet interfaces, and industrial controller modules requiring stable component supply, long-term lifecycle support, and RoHS-compliant packaging.
Supply support for TVS8814MUTAG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
onsemi (formerly ON Semiconductor) is a global semiconductor supplier specializing in energy-efficient power management, analog, sensing, and connectivity solutions for automotive, industrial, cloud, and consumer markets.
The TVS8814MUTAG belongs to onsemi's transient voltage suppressor product line, engineered specifically for high-speed data line protection in Ethernet, USB, and HDMI applications where low capacitance and precise clamping are critical.
FAQ
What is the maximum clamping voltage of TVS8814MUTAG at 35 A surge current?
The TVS8814MUTAG clamps to a maximum of 15 V at 35 A peak pulse current (8/20 µs waveform), as specified in the Electrical Characteristics table. This value ensures safe operation below the absolute maximum voltage ratings of standard Ethernet PHY ICs. The clamping behavior is verified per IEC 61000−4−5 testing, and TVS8814MUTAG maintains this performance across its full operating temperature range (−55 °C to +125 °C).
Does TVS8814MUTAG support bidirectional signal lines like Ethernet differential pairs?
Yes, TVS8814MUTAG is a unidirectional TVS array but functions effectively on bidirectional AC-coupled differential lines such as 100BASE-TX and 1000BASE-T. Its 3.0 V working peak reverse voltage aligns with typical 3.3 V PHY supplies, and its low dynamic resistance ensures symmetrical clamping during positive and negative transients. The device does not impede normal signal swing because it only conducts during overvoltage events exceeding its breakdown threshold (~3.2–5.0 V).
Can TVS8814MUTAG replace discrete TVS diodes in an existing Ethernet design?
Yes, TVS8814MUTAG replaces four discrete unidirectional TVS diodes in a single UDFN8 package. Its flow-thru pinout (Pins 2/3/6/7 as I/O, Pins 1/4/5/8 as GND) simplifies layout by enabling straight-through routing-eliminating vias and stubs. However, PCB footprint and solder mask must be updated to match the 2.2 × 2.0 mm UDFN8 outline and 0.575 mm pitch; thermal pad grounding must also be implemented per onsemi's mounting guidelines.
What is the I/O-to-GND junction capacitance of TVS8814MUTAG?
The I/O-to-GND junction capacitance of TVS8814MUTAG is 5.0 pF at 0 V bias and 1 MHz, as measured per the Electrical Characteristics table. This parameter affects common-mode filtering but does not impact differential signal integrity-the critical spec for Ethernet is I/O-to-I/O capacitance, which is guaranteed ≤2.0 pF and directly determines high-frequency insertion loss and return loss performance.
Is TVS8814MUTAG compliant with lead-free assembly standards?
Yes, TVS8814MUTAG is a Pb-free device rated for lead-free reflow soldering up to 260 °C (10 seconds), per the Maximum Ratings table. It complies with JEDEC J-STD-020 moisture sensitivity level (MSL) 1 and supports standard SnAgCu (SAC305) reflow profiles. The UDFN8 package includes an exposed copper thermal pad to enhance thermal dissipation during surge events and improve long-term reliability under repeated transient stress.
TVS8814MUTAG Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Package/Case:
- -
- Series:
- *
- Packaging:
- Bulk
- Product Status:
- Active
- Type:
- -
- Unidirectional Channels:
- -
- Bidirectional Channels:
- -
- Voltage - Reverse Standoff (Typ):
- -
- Voltage - Breakdown (Min):
- -
- Voltage - Clamping (Max) @ Ipp:
- -
- Current - Peak Pulse (10/1000µs):
- -
- Power - Peak Pulse:
- -
- Power Line Protection:
- -
- Applications:
- -
- Capacitance @ Frequency:
- -
- Operating Temperature:
- -
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- -
- Supplier Device Package:
- -
TVS8814MUTAG FAQ
1.How can I place an order for TVS8814MUTAG through Aetrix?
Please submit a Request for Quotation (RFQ) for TVS8814MUTAG on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TVS8814MUTAG reliable?
The price and inventory of TVS8814MUTAG are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TVS8814MUTAG is usually 5 days.
3.What payment methods are accepted for TVS8814MUTAG?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TVS8814MUTAG transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TVS8814MUTAG?
TVS8814MUTAG orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TVS8814MUTAG order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TVS8814MUTAG?
For technical support, including TVS8814MUTAG datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TVS8814MUTAG requirements.
6.How does Aetrix verify that TVS8814MUTAG is sourced from the original manufacturer or authorized distributors?
All TVS8814MUTAG products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TVS8814MUTAG meets industry standards.
7.What is the process for return or replacement of TVS8814MUTAG?
All TVS8814MUTAG units undergo pre-shipment inspection (PSI). If there is an issue with TVS8814MUTAG, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TVS8814MUTAG part is unused and in its original packaging.
Return procedure for TVS8814MUTAG:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
TVS8814MUTAG Tags

-
ESD9B5.0ST5G
onsemi

-
DESD3V3E1BL-7B
Diodes Incorporated

-
ESD5Z3.3T1G
onsemi

-
D5V0H1B2LP-7B
Diodes Incorporated

-
D5V0P1B2LP-7B
Diodes Incorporated

-
DESD5V0U1BA-7
Diodes Incorporated

-
ESD5Z5.0T1G
onsemi

-
DESD5V0U1BB-7
Diodes Incorporated

-
D12V0L1B2LP-7B
Diodes Incorporated

-
PESD2V0Y1BSFYL
Nexperia USA Inc.

-
DF2S5M4CT,L3F
Toshiba Semiconductor and Storage

-
D5V0L1B2WS-7
Diodes Incorporated
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

