STMicroelectronics USBLC6-2SC6Y
- Part No.:
- USBLC6-2SC6Y
- Manufacturer:
- STMicroelectronics
- Category:
- TVS Diodes
- Package:
- SOT-23-6
- Datasheet:
-
USBLC6-2SC6Y.pdf
- Description:
- TVS DIODE 5.25VWM 17VC SOT23-6
- Quantity:
- Payment:

- Shipping:

Inventory:38,766
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Product details
Overview
USBLC6-2SC6Y from STMicroelectronics is an automotive-grade monolithic ESD protection diode array designed for high-speed USB 2.0 data lines (D+/D−) and VBUS line protection. It delivers 2.5 pF typical I/O-to-GND capacitance, 10 nA leakage at 5.25 V, 6 V breakdown voltage, AEC-Q101 qualification, and ISO10605 ±25 kV air discharge robustness. It secures signal integrity in 480 Mb/s USB interfaces while protecting sensitive transceivers.
For engineers reviewing the USBLC6-2SC6Y datasheet, USBLC6-2SC6Y pinout, USBLC6-2SC6Y application, or USBLC6-2SC6Y equivalent, key selection criteria include interline capacitance matching (±0.015 pF), clamping voltage (12 V @ 1 A), VBUS protection capability, SOT23-6L footprint compatibility, and automotive reliability validation per AEC-Q101.
Technical Context
The device integrates six bidirectional Transil™ diodes in a single SOT23-6L package: two dedicated to D+ and D− lines (each with matched 2.5 pF capacitance to GND), one for VBUS protection, and shared GND paths. Its low dynamic impedance ensures sub-1 ns response to ESD transients.
Capacitance matching between D+ and D− (ΔCI/O–GND ≤ 0.015 pF) and interline capacitance (CI/O–I/O = 1.2–1.7 pF) are tightly controlled to preserve differential signal balance required by USB 2.0 high-speed eye diagram compliance.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| ESD Rating (ISO10605) | ±25 kV air discharge, ±15 kV contact discharge - guarantees system-level immunity without external TVS stacking |
| I/O-to-GND Capacitance | 2.5 pF typ. @ 1.65 V - enables full USB 2.0 480 Mb/s signaling without jitter or rise-time degradation |
| Interline Capacitance Matching | ±0.015 pF - maintains D+/D− skew < 0.5 ps for compliant differential timing |
| Leakage Current | 10 nA max. @ 5.25 V - prevents bus loading and standby power loss in battery-powered USB peripherals |
| Clamping Voltage | 12 V @ 1 A (8/20 µs) - limits transient overvoltage below 13.3 V logic rail tolerance of common USB PHYs |
| Breakdown Voltage | 6 V min. @ 1 mA - provides safe margin above 5.25 V VBUS max., preventing false triggering during ripple |
| Operating Junction Temp | –40 °C to +150 °C - supports under-hood automotive deployment without derating |
Pinout & Package
SOT23-6L package (JEDEC MO178AB), 3.05 mm × 1.75 mm × 1.30 mm, lead-free, RoHS-compliant, UL94 V0 epoxy.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | D+ I/O | Protected high-speed data line input/output; bidirectionally clamped to GND and VBUS |
| 2 | GND | Common reference for all ESD paths; must be low-inductance PCB connection |
| 3 | VBUS | 5 V supply line protection node; clamped to GND via high-energy diode |
| 4 | GND | Second GND terminal for symmetric layout; reduces ground loop inductance |
| 5 | D− I/O | Complementary protected data line; capacitance and leakage matched to Pin 1 within 0.015 pF/10 nA |
| 6 | No Connect | Internally unconnected; left floating per ST design - no PCB trace or solder mask opening required |
Key Features
| Feature | Design Value |
|---|---|
| Monolithic dual-line protection | Single-die integration of D+/D−/VBUS protection eliminates discrete component count and layout mismatch |
| USB 2.0 signal integrity optimization | 2.5 pF I/O–GND + 1.2 pF I/O–I/O + ±0.015 pF matching meets USB-IF eye mask requirements at 480 Mb/s |
| AEC-Q101 qualification | Validated for automotive temperature cycling, HAST, and mechanical shock - suitable for junction box and infotainment ports |
| Low-leakage VBUS clamp | 10 nA IR at 5.25 V prevents >1 µW standby dissipation in always-on USB host ports |
| Robust ISO7637-3 pulse immunity | Withstands –150 V Pulse 3a and +100 V Pulse 3b surges - protects against load dump and inductive switching noise |
Applications
| USB 2.0 High-Speed Port | Automotive Smart Junction Box |
|---|---|
Use Scenario: Front/rear USB charging and data sync port in vehicle head unit or center console. IC Role / Device Role / Timing Role: Primary ESD interface protector on D+/D− and VBUS lines before USB PHY IC. Use Value: Maintains 480 Mb/s eye opening while surviving repeated ±25 kV ESD events during user cable insertion. | Use Scenario: Centralized USB hub distributing power and data to multiple cabin modules (e.g., rear-seat entertainment, telematics). IC Role / Device Role / Timing Role: Line-level surge suppressor at each USB branch output, ensuring fault isolation across domains. Use Value: Prevents single-point ESD failure from propagating to entire junction box; AEC-Q101 ensures 15-year field reliability. |
| Ethernet 10/100 Base-T Port | Video Interface Protection |
Use Scenario: In-vehicle Ethernet link connecting ADAS camera to domain controller over twisted-pair cabling. IC Role / Device Role / Timing Role: Common-mode ESD shunt on differential pair, referenced to chassis GND. Use Value: 1.2 pF interline capacitance avoids signal attenuation beyond IEEE 802.3u return loss limits at 31.25 MHz. | Use Scenario: LVDS or FPD-Link video path from display processor to TFT panel in digital instrument cluster. IC Role / Device Role / Timing Role: Low-capacitance transient suppressor on clock and data lanes to preserve edge rate. Use Value: Sub-1.7 pF I/O–I/O capacitance prevents >5% rise-time degradation critical for 1.5 Gbps pixel clock fidelity. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar ESD protection applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPD2EUSB30DRYR | 0.7 pF I/O–GND, but only protects D+/D− (no VBUS clamp); 3-pin X2SON | Lacks integrated VBUS protection - requires external 5 V TVS; better for space-constrained USB-only designs | Select when board area is critical and VBUS protection is handled separately |
| ESD56201D05 | 3.0 pF I/O–GND, 15 kV ISO10605 rating, SOT23-6 package | Lower ESD rating and higher capacitance - acceptable for USB 1.1/full-speed only, not high-speed compliant | Select for cost-sensitive non-automotive USB 2.0 peripherals where AEC-Q101 is unnecessary |
Compared with TPD2EUSB30DRYR and ESD56201D05, USBLC6-2SC6Y uniquely combines VBUS clamping, AEC-Q101 qualification, and 2.5 pF/±0.015 pF performance-making it the only choice for automotive USB 2.0 high-speed ports requiring single-component, production-ready ESD immunity.
Availability
USBLC6-2SC6Y is available at Aetrix Electronics and suitable for automotive infotainment systems, smart junction boxes, and industrial USB host interfaces requiring stable component supply across extended temperature ranges and long product lifecycles.
Supply support for USBLC6-2SC6Y includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power ICs, sensors, and protection devices for automotive, industrial, and consumer markets.
The USBLC series targets high-speed interface protection with monolithic Transil architecture, specifically engineered to meet USB-IF, AEC-Q101, and ISO10605 requirements without compromising signal fidelity.
FAQ
What is the maximum recommended PCB trace length between USBLC6-2SC6Y and the protected USB connector?
ST recommends ≤8 mm from device pins to connector pads for D+/D− lines. Longer traces increase inductance, degrading ESD clamping effectiveness and causing resonance above 500 MHz. The GND connections must use multiple vias directly beneath the SOT23-6L footprint to minimize ground bounce during 25 kV transients.
Does USBLC6-2SC6Y require external biasing or control signals?
No. USBLC6-2SC6Y is a passive, unidirectional clamping device with no enable pin, supply voltage, or configuration interface. It operates solely via avalanche breakdown of integrated silicon diodes and requires zero external components for basic ESD protection functionality.
Can USBLC6-2SC6Y protect USB 3.0 SuperSpeed differential pairs?
No. Its 2.5 pF I/O–GND capacitance and 1.7 pF I/O–I/O capacitance exceed USB 3.0's <0.3 pF requirement for 5 Gbps operation. It is explicitly rated for USB 2.0 (480 Mb/s) and lower-speed protocols only, as confirmed in ST's AN2689 application note and datasheet Figure 4.
How does the NC (Pin 6) terminal affect PCB layout?
Pin 6 is internally unconnected and must remain floating - no copper pour, trace, or solder mask opening should contact it. ST specifies this to prevent parasitic coupling that could degrade interline capacitance matching. Standard SOT23-6L footprints with isolated pad 6 comply fully with this requirement.
USBLC6-2SC6Y Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Package/Case:
- SOT-23-6
- Series:
- USBY
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Type:
- Steering (Rail to Rail)
- Unidirectional Channels:
- 2
- Bidirectional Channels:
- -
- Voltage - Reverse Standoff (Typ):
- 5.25V
- Voltage - Breakdown (Min):
- 6V
- Voltage - Clamping (Max) @ Ipp:
- 17V
- Current - Peak Pulse (10/1000µs):
- 5A (8/20µs)
- Power - Peak Pulse:
- -
- Power Line Protection:
- Yes
- Applications:
- Ethernet
- Capacitance @ Frequency:
- -
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- Automotive
- Qualification:
- AEC-Q101
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- SOT-23-6
USBLC6-2SC6Y FAQ
1.How can I place an order for USBLC6-2SC6Y through Aetrix?
Please submit a Request for Quotation (RFQ) for USBLC6-2SC6Y on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for USBLC6-2SC6Y reliable?
The price and inventory of USBLC6-2SC6Y are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for USBLC6-2SC6Y is usually 5 days.
3.What payment methods are accepted for USBLC6-2SC6Y?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for USBLC6-2SC6Y transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for USBLC6-2SC6Y?
USBLC6-2SC6Y orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your USBLC6-2SC6Y order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for USBLC6-2SC6Y?
For technical support, including USBLC6-2SC6Y datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your USBLC6-2SC6Y requirements.
6.How does Aetrix verify that USBLC6-2SC6Y is sourced from the original manufacturer or authorized distributors?
All USBLC6-2SC6Y products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that USBLC6-2SC6Y meets industry standards.
7.What is the process for return or replacement of USBLC6-2SC6Y?
All USBLC6-2SC6Y units undergo pre-shipment inspection (PSI). If there is an issue with USBLC6-2SC6Y, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The USBLC6-2SC6Y part is unused and in its original packaging.
Return procedure for USBLC6-2SC6Y:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
USBLC6-2SC6Y Tags

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