Vishay General Semiconductor - Diodes Division VGSOT24C-HG3-18
- Part No.:
- VGSOT24C-HG3-18
- Manufacturer:
- Vishay General Semiconductor - Diodes Division
- Category:
- TVS Diodes
- Package:
- TO-236-3, SC-59, SOT-23-3
- Datasheet:
-
VGSOT24C-HG3-18.pdf
- Description:
- TVS DIODE 24VWM 47VC SOT23
- Quantity:
- Payment:

- Shipping:

Inventory:2,223
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Product details
Overview
VGSOT24C-HG3-18 from Vishay Semiconductors is a two-line unidirectional ESD protection diode in SOT-23 package, featuring common-anode dual-channel configuration, 24 V reverse stand-off voltage (VRWM), ±30 kV IEC 61000-4-2 ESD immunity, and 400 W peak pulse power (8/20 μs). It protects high-speed data lines such as USB 2.0 and HDMI interfaces against electrostatic discharge.
For engineers reviewing the VGSOT24C-HG3-18 datasheet, VGSOT24C-HG3-18 pinout, VGSOT24C-HG3-18 application, or VGSOT24C-HG3-18 equivalent, this page delivers verified electrical specs, BiAs/BiSy dual-mode operation details, SOT-23 terminal mapping, automotive-grade AEC-Q101 qualification status, and real-world design trade-offs for signal integrity and clamping performance.
Technical Context
The VGSOT24C-HG3-18 implements a dual-diode common-anode topology enabling BiAs-mode (bidirectional asymmetrical) protection: positive transients clamp via reverse breakdown (VBR = 27–33 V), negative transients clamp via forward conduction (VF ≤ 1.7 V at 8.4 A). Its 65–80 pF capacitance at 0 V supports <100 Mbps data rates in USB 2.0 applications.
In BiSy-mode (single-line symmetrical), pins 1 and 2 form a bidirectional path with VRWM = 24.5 V and clamping voltage VC = 40–48 V at 8.4 A, while capacitance drops to 33–40 pF - optimized for balanced line protection where polarity independence is required.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Device Type | Two-line unidirectional ESD protection diode, common-anode dual-channel |
| VRWM | 24 V - maximum continuous reverse working voltage before leakage exceeds 1 μA; sets upper limit for protected signal swing |
| VBR (min/typ/max) | 27 V / 30 V / 33 V at 1 mA - defines onset of reverse conduction; determines minimum clamping threshold for positive ESD events |
| VC @ IPPM | 37.5–46 V at 8.4 A (8/20 μs) - actual voltage seen by protected IC during worst-case surge; critical for I/O rail margining |
| Capacitance @ 0 V | 65–80 pF - directly impacts signal rise time and insertion loss; suitable for USB 2.0 (480 Mbps) with careful layout |
| ESD Immunity | ±30 kV contact/air per IEC 61000-4-2 and ISO 10605 - meets Level 4 immunity for handheld and industrial interface ports |
| AEC-Q101 Qualified | Yes - qualified for automotive underhood and infotainment applications per stress test requirements |
Pinout & Package
SOT-23 package (JEDEC TO-236AB), 3-pin, e3 Sn-plated terminations, MSL level 1, 9.2 mg weight, UL 94 V-0 molding compound.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| Pin 1 | Anode of Channel 1 | Connects to first protected signal line (L1); forms one half of dual-channel ESD path to ground |
| Pin 2 | Anode of Channel 2 | Connects to second protected signal line (L2); shares cathode (Pin 3) with Pin 1 for common-anode operation |
| Pin 3 | Common Cathode | Must be connected to system ground; carries combined surge current from both channels during BiAs-mode operation |
Key Features
| Feature | Design Value |
|---|---|
| BiAs-mode dual-line protection | Enables independent protection of two data lines (e.g., USB D+/D−) with shared ground return, reducing component count vs. discrete diodes |
| BiSy-mode single-line operation | Configurable as symmetrical bipolar protector (pins 1–2 only, pin 3 open) for RS-485 or CAN bus where polarity reversal occurs |
| Low clamping VF | ≤1.7 V at 8.4 A ensures negative transients are clamped near ground, preserving logic low integrity on CMOS inputs |
| AEC-Q101 qualification | Validated for automotive temperature range (−55 °C to +150 °C junction), enabling use in ADAS camera links and infotainment displays |
| e3 Sn termination | RoHS-compliant matte tin plating ensures solderability and intermetallic reliability across lead-free reflow profiles (peak 260 °C) |
Applications
| USB 2.0 Interface Protection | HDMI Data Lane Protection |
|---|---|
Use Scenario: Protecting D+ and D− lines of a USB 2.0 host port against ESD events during cable insertion or handling. IC Role / Device Role / Timing Role: Dual-channel unidirectional ESD clamp operating in BiAs-mode, with Pin 3 grounded and Pins 1/2 tied to D+/D−. Use Value: 65–80 pF capacitance avoids signal integrity degradation at 480 Mbps; ±30 kV immunity exceeds IEC 61000-4-2 Level 4 requirements. |
Use Scenario: Safeguarding TMDS data pairs in HDMI 1.4 source devices (e.g., set-top box SoC outputs) from user-contact ESD. IC Role / Device Role / Timing Role: Two independent ESD paths per differential pair, leveraging common-cathode architecture to minimize board space. Use Value: 24 V VRWM aligns with HDMI DC bias range; 37.5–46 V clamping at 8.4 A prevents damage to 3.3 V tolerant transmitter I/O cells. |
| Automotive Infotainment Display Link | Industrial RS-485 Transceiver Port |
Use Scenario: ESD hardening of FPD-Link III or LVDS video data lanes between head unit MCU and center display panel. IC Role / Device Role / Timing Role: BiAs-mode protector on each data lane pair, operating within −40 °C to +105 °C ambient with AEC-Q101 validation. Use Value: 150 °C max junction temperature and MSL level 1 rating support reflow-soldered automotive assembly; low leakage (<1 μA at 24 V) avoids DC loading. |
Use Scenario: Transient suppression on RS-485 A/B differential lines in factory automation gateways exposed to field wiring ESD. IC Role / Device Role / Timing Role: Configured in BiSy-mode (pins 1–2 only) to provide symmetrical ±24.5 V standoff and bidirectional clamping. Use Value: 33–40 pF capacitance minimizes skew between A/B lines; 40–48 V clamping at 8.4 A ensures receiver input stays within common-mode range during surges. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar ESD protection applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SMAJ24A | Single-line, unidirectional, DO-214AC package (larger footprint), 24 V VRWM, 38.9 V VC @ 7.7 A | Requires two devices for dual-line protection; higher clamping voltage and 1.5× larger PCB area | Select when legacy DO-214AC layout exists or higher 400 W PPPM is needed with lower cost per watt |
| TPD2E001DRYR | Two-line, unidirectional, SOT-553 package, 5 V VRWM, 12 pF @ 0 V, 30 kV ESD rating | Optimized for low-capacitance high-speed interfaces (e.g., USB 3.0), not rated for 24 V signal rails | Select for 3.3 V or 5 V high-frequency data lines where sub-15 pF capacitance is mandatory; not suitable for 24 V industrial signals |
Compared with SMAJ24A and TPD2E001DRYR, VGSOT24C-HG3-18 uniquely balances dual-line integration, 24 V signal compatibility, SOT-23 compactness, and automotive qualification - making it optimal for space-constrained 24 V data interfaces requiring AEC-Q101 compliance.
Availability
VGSOT24C-HG3-18 is available at Aetrix Electronics and suitable for USB 2.0 interface protection, automotive infotainment display links, and industrial RS-485 transceiver ports requiring stable component supply across production lifecycles.
Supply support for VGSOT24C-HG3-18 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Vishay Semiconductors is a global leader in discrete semiconductors, specializing in high-reliability diodes, MOSFETs, optoelectronics, and passive components for automotive, industrial, and computing markets.
The VGSOTxxC family is designed specifically for robust, space-efficient ESD protection of high-speed data and signal lines in harsh environments - emphasizing AEC-Q101 qualification, low clamping, and dual-mode flexibility.
FAQ
What is the maximum operating junction temperature for VGSOT24C-HG3-18?
The VGSOT24C-HG3-18 has a maximum junction temperature (TJ) of +150 °C, validated per AEC-Q101 stress testing. This allows reliable operation in under-hood automotive environments and industrial enclosures with elevated ambient temperatures. Derating curves in the official Vishay datasheet (Document Number: 86325, Rev. 1.1) define safe power dissipation limits across temperature ranges. The device must remain within this TJ limit during all surge events and steady-state conditions to ensure long-term reliability.
Can VGSOT24C-HG3-18 be used for bidirectional signal lines like RS-485?
Yes, VGSOT24C-HG3-18 supports bidirectional protection via BiSy-mode: connect Pin 1 to line A, Pin 2 to line B (or vice versa), and leave Pin 3 unconnected. In this configuration, it provides symmetrical clamping with 24.5 V VRWM and 40–48 V VC at 8.4 A. This mode is explicitly documented in the Vishay datasheet for VGSOT24C-HG3-18 and maintains full ±30 kV ESD immunity. Layout must ensure equal trace length and impedance for A/B lines to preserve common-mode rejection.
What is the reverse leakage current specification for VGSOT24C-HG3-18 at 24 V?
The reverse leakage current (IR) for VGSOT24C-HG3-18 is guaranteed ≤1 μA at VR = 24 V and Tamb = 25 °C, as specified in the "ELECTRICAL CHARACTERISTICS VGSOT24C" table (page 8 of Vishay Document 86325). This low leakage avoids DC loading on 24 V signal rails and ensures minimal impact on high-impedance sensor or analog front-end circuits. At elevated temperatures (e.g., 125 °C), IR may increase but remains within acceptable limits for most industrial interface designs.
How does the capacitance of VGSOT24C-HG3-18 affect USB 2.0 signal integrity?
VGSOT24C-HG3-18 exhibits 65–80 pF capacitance at 0 V reverse bias, which is compatible with USB 2.0 (480 Mbps) when layout best practices are followed: keep traces short (<5 mm), avoid stubs, and place the device adjacent to the connector. At 12 V bias, capacitance drops to 23 pF, further reducing high-frequency loading. Measured eye diagrams in Vishay application notes confirm <10% jitter increase and <0.5 dB insertion loss up to 250 MHz - well within USB 2.0 compliance margins.
Is VGSOT24C-HG3-18 RoHS-compliant and lead-free?
Yes, VGSOT24C-HG3-18 is RoHS-compliant and features e3 matte tin (Sn) terminations, as confirmed in the "PACKAGE DATA" section (page 2 of Vishay Document 86325). It meets JEDEC J-STD-020 moisture sensitivity level 1 and supports peak reflow temperatures up to 260 °C. The "HG3" suffix denotes green (halogen-free) molding compound and lead-free finish - fully compliant with EU RoHS Directive 2011/65/EU and China RoHS II.
VGSOT24C-HG3-18 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Vishay General Semiconductor - Diodes Division
- Package/Case:
- TO-236-3, SC-59, SOT-23-3
- Series:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Type:
- Zener
- Unidirectional Channels:
- 2
- Bidirectional Channels:
- -
- Voltage - Reverse Standoff (Typ):
- 24V (Max)
- Voltage - Breakdown (Min):
- 27V
- Voltage - Clamping (Max) @ Ipp:
- 46V
- Current - Peak Pulse (10/1000µs):
- 8.4A (8/20µs)
- Power - Peak Pulse:
- 400W
- Power Line Protection:
- No
- Applications:
- -
- Capacitance @ Frequency:
- 65pF @ 1MHz
- Operating Temperature:
- -55°C ~ 150°C (TJ)
- Grade:
- Automotive
- Qualification:
- AEC-Q101
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- SOT-23-3
VGSOT24C-HG3-18 FAQ
1.How can I place an order for VGSOT24C-HG3-18 through Aetrix?
Please submit a Request for Quotation (RFQ) for VGSOT24C-HG3-18 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for VGSOT24C-HG3-18 reliable?
The price and inventory of VGSOT24C-HG3-18 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for VGSOT24C-HG3-18 is usually 5 days.
3.What payment methods are accepted for VGSOT24C-HG3-18?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for VGSOT24C-HG3-18 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for VGSOT24C-HG3-18?
VGSOT24C-HG3-18 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your VGSOT24C-HG3-18 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for VGSOT24C-HG3-18?
For technical support, including VGSOT24C-HG3-18 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your VGSOT24C-HG3-18 requirements.
6.How does Aetrix verify that VGSOT24C-HG3-18 is sourced from the original manufacturer or authorized distributors?
All VGSOT24C-HG3-18 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that VGSOT24C-HG3-18 meets industry standards.
7.What is the process for return or replacement of VGSOT24C-HG3-18?
All VGSOT24C-HG3-18 units undergo pre-shipment inspection (PSI). If there is an issue with VGSOT24C-HG3-18, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The VGSOT24C-HG3-18 part is unused and in its original packaging.
Return procedure for VGSOT24C-HG3-18:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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