Nexperia USA Inc. BSP130,115

Overview

BSP130,115 from Nexperia (formerly Philips Semiconductors) is an N-channel enhancement-mode vertical D-MOS transistor in SOT223 package, rated for 300 V drain-source voltage, 350 mA DC drain current, and 1.5 W total power dissipation at 25 °C ambient. It features 3.7 Ω R_DS(on) at V_GS = 10 V and I_D = 250 mA, gate threshold voltage of 0.8–2 V, and sub-10 ns turn-on time - optimized for line current interruption and high-speed transformer driving in telecom terminal equipment.

For engineers reviewing the BSP130,115 datasheet, BSP130,115 pinout, BSP130,115 application, or BSP130,115 equivalent, key selection criteria include its 300 V blocking capability, low gate charge enabling direct CMOS/TTL interface, absence of secondary breakdown, and thermal resistance of 83.3 K/W on standard PCB mounting - critical for reliable relay and telephone line driver designs.

Technical Context

This discrete MOSFET employs a vertical D-MOS structure to achieve high-voltage operation without secondary breakdown limitations, supporting robust switching under inductive loads. Its gate threshold voltage range (0.8–2 V) ensures compatibility with low-voltage logic families while maintaining noise immunity.

Static characteristics are specified at T_j = 25 °C, with dynamic parameters including 6–10 ns turn-on time and 46–60 ns turn-off time at V_DD = 50 V and I_D = 250 mA. Input capacitance (C_iss) is 100–120 pF, output capacitance (C_oss) 21–30 pF, and feedback capacitance (C_rss) 10–15 pF at V_DS = 25 V and f = 1 MHz.

Key Specifications

Pinout & Package

SOT223 (SC-73) surface-mount plastic package with integrated drain tab for enhanced thermal conduction; 4-lead configuration with exposed drain pad (Pin 2 and Pin 4 both connected to drain).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar N-channel high-voltage MOSFET applications.

Compared with BSP129,115, the BSP130,115 provides essential 300 V surge tolerance for telephone line applications; versus BUK452-60R, it offers compact SOT223 footprint and lower gate drive demand at the cost of current and voltage headroom.

Availability

BSP130,115 is available at Aetrix Electronics and suitable for telephone line interface modules, relay driver circuits, and line transformer driver designs requiring stable component supply and long-term industrial availability.

Supply support for BSP130,115 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia - formerly Philips Semiconductors - is a global leader in discrete, logic, and MOSFET solutions, specializing in high-volume, high-reliability semiconductor components for automotive, industrial, and consumer applications.

The BSP130,115 belongs to Nexperia's legacy high-voltage logic-level MOSFET product line, engineered specifically for telecom infrastructure and low-power switching applications demanding ruggedness, fast switching, and direct logic interfacing.

FAQ

What is the maximum continuous drain current for BSP130,115 at 70 °C ambient temperature?

The BSP130,115 has a DC drain current rating of 350 mA at T_amb ≤25 °C. At 70 °C ambient, derating applies per the power derating curve: P_tot drops linearly from 1.5 W at 25 °C to 0 W at 150 °C junction temperature. With R_{th j-a} = 83.3 K/W, maximum allowable I_D at 70 °C ambient is approximately 220 mA to maintain T_j ≤150 °C.

Can BSP130,115 be used in avalanche energy applications?

Yes - the BSP130,115 is characterized for unclamped inductive switching (UIS) and exhibits no secondary breakdown, making it suitable for controlled avalanche operation in line transformer flyback recovery. The SOAR curve (Fig.11) confirms safe single-pulse avalanche capability up to 100 V and 1 A for 10 µs pulses at 25 °C ambient.

Is the SOT223 drain tab internally connected to both Pin 2 and Pin 4?

Yes - the datasheet explicitly states "Pin 2 drain" and "Pin 4 drain", and the mechanical outline shows both pins electrically and thermally tied to the same exposed drain pad. This dual-drain configuration improves current sharing and thermal spreading across the PCB copper area.

What is the typical gate charge required to fully enhance BSP130,115?

While Q_g is not directly specified, gate charge can be inferred from C_iss = 100–120 pF and V_GS swing of 10 V: Q_g ≈ C_iss × ΔV_GS ≈ 1.2 nC. This low gate charge enables direct drive from microcontroller GPIOs or logic gates without external buffers, consistent with its "direct interface to CMOS/TTL" feature.