Diodes Incorporated DMT3011LDT-7

Overview

DMT3011LDT-7 from Diodes Incorporated is a dual N-channel enhancement-mode MOSFET in a V-DFN3030-8 (Type K) package, rated for 30V V_DS, with Q1 R_DS(ON) = 20 mΩ @ 10V and Q2 R_DS(ON) = 11.1 mΩ @ 10V, delivering 6.3A/9.6A continuous drain current at 4.5V gate drive - optimized for high-efficiency point-of-load regulation in mobile computing power rails.

For engineers reviewing the DMT3011LDT-7 datasheet, DMT3011LDT-7 pinout, DMT3011LDT-7 application, or DMT3011LDT-7 equivalent, key selection criteria include dual-channel thermal coupling, low-profile 0.6mm height, 4mm² PCB footprint, asymmetric channel ratings, and validated body diode recovery (t_RR = 11.4 ns / 18 ns) for synchronous buck topologies.

Technical Context

This dual MOSFET integrates two discrete N-channel silicon devices in a single lead-free V-DFN3030-8 package with shared thermal pad and independent gate/drain/source terminals. Q1 and Q2 feature distinct R_DS(ON) and current ratings - Q2 optimized for higher-current output stage, Q1 for control or auxiliary switching - enabling compact dual-phase or input/output switching configurations.

Gate threshold voltage (1–3 V) and low total gate charge (Q_g = 13.2 nC / 13.8 nC at 10 V) support direct drive from 3.3 V and 5 V controllers. Dynamic parameters including C_iss (641 pF / 748 pF), Cr_ss (50 pF / 43 pF), and fast switching times (t_F = 5.3 ns / 1.4 ns) are specified under defined test conditions (V_DS = 15 V, I_D = 1 A / 10 A, R_G = 6 Ω / 1 Ω).

Key Specifications

Pinout & Package

V-DFN3030-8 (Type K) package with exposed thermal pad (pin 5), 0.65 mm pitch, 3.0 mm × 3.0 mm body, and NiPdAu-plated copper leadframe. Bottom-view pin numbering starts at top-left corner (pin 1), counterclockwise.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual N-channel MOSFET applications.

Compared with DMT3011LDT-7, DMT3012LDT-7 offers lower R_DS(ON) at minor cost increase and identical form factor, while SI6926ADQ-T1-GE3 trades thermal performance and footprint for through-hole assembly compatibility and higher V_DS margin.

Availability

DMT3011LDT-7 is available at Aetrix Electronics and suitable for mobile computing power delivery, USB-C PD interface switching, and industrial IoT sensor hub designs requiring stable component supply, consistent parametric performance, and long-term lifecycle support.

Supply support for DMT3011LDT-7 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Diodes Incorporated is a global manufacturer of discrete semiconductors and analog ICs, headquartered in Plano, Texas, with design centers across Asia and manufacturing in China, Taiwan, and the U.S.

The DMT series targets high-density power management in portable electronics, emphasizing low R_DS(ON), minimal profile, and robust thermal performance in advanced DFN packages.

FAQ

What is the maximum continuous drain current for each channel at 85°C ambient?

At T_A = 85°C, derating applies: Q1 delivers 4.5 A and Q2 delivers 6.8 A (based on R_θJA = 65 °C/W, P_D = 1.9 W, and T_J(MAX) = 150°C). These values assume 1-inch² 2 oz copper PCB and no forced airflow.

Can pin 1 (S1/D2) be used as a floating node in non-cascode configurations?

No - pin 1 is internally bonded to both Q1 source and Q2 drain; it must be connected to either ground (for low-side Q2 operation) or the switching node (for high-side Q1 use). Leaving it unconnected violates absolute maximum ratings and risks latch-up.

Is the thermal pad (pin 5) electrically isolated from all other terminals?

Yes - the exposed thermal pad is a dedicated copper slug with no internal electrical connection. It must be soldered to a PCB thermal plane and may be left floating or tied to system ground depending on EMI and safety requirements.

How does the gate threshold variation affect drive circuit design across temperature?

V_GS(TH) shifts from ~1.4 V at -55°C to ~2.6 V at +150°C (Fig. 20); drive circuits must ensure ≥3.5 V gate voltage across full temperature range to guarantee full enhancement, especially at cold start.