Diodes Incorporated DMT35M8LDG-7

Overview

DMT35M8LDG-7 from Diodes Incorporated is an asymmetric dual N-channel MOSFET in PowerDI3333-8 (Type G) package, integrating two discrete enhancement-mode silicon MOSFETs with distinct R_DS(ON) and current ratings: Q1 delivers 4.7 mΩ @ 10 V (17.0 A), Q2 offers 5.8 mΩ @ 10 V (15.3 A), both rated for 30 V V_DSS. It serves as a compact, high-efficiency synchronous rectifier or half-bridge switch in DC-DC converters.

For engineers reviewing the DMT35M8LDG-7 datasheet, DMT35M8LDG-7 pinout, DMT35M8LDG-7 application, or DMT35M8LDG-7 equivalent, key selection criteria include asymmetric conduction capability, low gate charge (Q_g = 22.7 nC / 16.3 nC), thermal resistance (R_θJC = 12.1 °C/W), and PowerDI3333-8 thermal pad layout compatibility.

Technical Context

This device implements two independent N-channel enhancement-mode MOSFETs sharing a common source terminal (S1/S2 tied internally per pinout), enabling asymmetric current handling in buck converter topologies where high-side and low-side switches require different on-resistance and charge trade-offs. Its design targets minimal R_DS(ON) at 4.5 V and 10 V drive while maintaining fast switching (t_F = 3.9 ns / 4.3 ns).

The PowerDI3333-8 package features an exposed drain pad for thermal dissipation, with R_θJC = 12.1 °C/W measured to the case, supporting continuous operation up to T_J = +150 °C. Dynamic parameters-C_iss = 1510 pF / 1032 pF, C_rss = 49 pF / 38 pF-are optimized to reduce Miller effect and improve gate drive efficiency in high-frequency power stages.

Key Specifications

Pinout & Package

Package: PowerDI3333-8 (Type G), surface-mount, thermally enhanced with exposed drain pad (pins 1, 4, 5, 8 connected to D1/D2). Dimensions: 3.30 mm × 3.30 mm × 0.80 mm (L × W × H), moisture sensitivity level 1.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual N-channel MOSFET applications.

Compared with DMT35M8LDGQ, the -7 version omits automotive qualification but retains identical R_DS(ON), Q_g, and thermal performance-making it optimal for cost-sensitive industrial and computing applications. Versus DMN3029LSD-13, the PowerDI3333-8 package delivers 2.3× lower R_θJC, enabling 2.1× higher continuous current in thermally constrained layouts.

Availability

DMT35M8LDG-7 is available at Aetrix Electronics and suitable for server VRM power stages, USB-C PD adapters, automotive ADAS camera modules, and industrial PLC I/O power supplies requiring stable component supply across multi-year production cycles.

Supply support for DMT35M8LDG-7 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Diodes Incorporated is a global manufacturer of discrete semiconductors and analog ICs, specializing in high-efficiency power management solutions for computing, industrial, and automotive markets.

The PowerDI3333-8 MOSFET product line targets high-density, thermally demanding DC-DC conversion-designed to replace discrete dual-MOSFET layouts with integrated asymmetric or matched pairs while preserving thermal and electrical performance.

FAQ

What is the maximum continuous drain current for Q1 and Q2 at 70°C ambient?

At T_A = +70°C, Q1 supports 13.6 A and Q2 supports 12.3 A with V_GS = 10 V, as specified in the Absolute Maximum Ratings table. These values assume FR-4 PCB mounting with 2 oz copper and thermal bias to a 1-inch square copper plate, and derate linearly from the +25°C ratings of 17.0 A and 15.3 A respectively.

Can pins 3 and 8 be used simultaneously for Q2 drain connection?

Yes-pins 3 and 8 are both labeled D2/S1 and electrically connected to the same internal node: the drain of Q2 and the shared source node. Using both pins reduces current density and package inductance, improving high-frequency switching performance and thermal spreading across the exposed drain pad.

Is the common source connection (S1/S2) accessible externally for gate drive referencing?

Yes-pins 2 (S1) and 7 (S2) are separate external terminals tied internally to the common source node. This allows independent Kelvin sensing or gate driver ground referencing, critical for accurate high-side gate drive in half-bridge configurations where source potential swings rapidly.

Does the device support 4.5 V logic-level gate drive for both channels?

Yes-both Q1 and Q2 are fully characterized at V_GS = 4.5 V: R_DS(ON) is 5.7 mΩ (Q1) and 7.3 mΩ (Q2), with corresponding I_D ratings of 15.5 A and 13.7 A. This enables direct interfacing with 3.3 V/5 V microcontroller GPIOs or standard PWM controllers without level-shifting.