Infineon Technologies IRF7380PBF

Overview

IRF7380PBF from Infineon Technologies is a dual N-channel enhancement-mode HEXFET^® Power MOSFET in SO-8 package, rated for 80 V V_DSS, 73 mΩ R_DS(on) at V_GS = 10 V, and 3.6 A continuous drain current. It integrates two independent MOSFETs with co-packaged body diodes, optimized for high-frequency DC-DC converters requiring low gate-to-drain charge (Q_gd = 4.5 nC) and fully characterized effective output capacitance (C_{oss_eff} = 140 pF).

For engineers reviewing the IRF7380PBF datasheet, IRF7380PBF pinout, IRF7380PBF application, or IRF7380PBF equivalent, key selection criteria include its dual-channel SO-8 layout, avalanche-rated operation (E_AS = 75 mJ), low Q_g (15–23 nC), temperature-stable R_DS(on) (±20% over −55°C to +150°C), and validated unclamped inductive switching performance.

Technical Context

This dual MOSFET implements two independent N-channel silicon power switches sharing a common SO-8 thermally enhanced leadframe. Each channel features a fully specified body diode with trr = 50 ns and Q_rr = 110 nC, enabling synchronous rectification in buck converters without external diodes.

Its dynamic parameters-including C_iss = 660 pF, C_oss = 110 pF, and Crss = 15 pF-are measured at 1 MHz and V_GS = 0 V, supporting accurate hard-switching loss modeling. The device is characterized for linear-mode operation up to 100°C ambient and supports repetitive avalanche stress per JEDEC JESD24-11.

Key Specifications

Pinout & Package

IRF7380PBF uses an SO-8 surface-mount package with exposed drain pad for thermal enhancement. Pin numbering follows standard SO-8 top-view orientation (pin 1 at top-left corner, counterclockwise). Both channels share no internal connection-D1/G1/S1 and D2/G2/S2 are electrically isolated.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual N-channel power MOSFET applications.

Compared with Si7852DP-T1-GE3 and DMN3026LSD-13, IRF7380PBF uniquely balances 80 V blocking capability with sub-5 nC Q_gd and validated avalanche performance-making it the only option among the three qualified for 48 V telecom and industrial DC-DC converters subject to line transients.

Availability

IRF7380PBF is available at Aetrix Electronics and suitable for high-frequency buck converters, synchronous rectifier stages, industrial motor driver half-bridges, and hot-swap controller protection FETs requiring stable component supply and long-term industrial lifecycle support.

Supply support for IRF7380PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Infineon Technologies is a German semiconductor manufacturer specializing in power management, automotive electronics, and industrial control ICs, with global manufacturing and qualification to AEC-Q101 and industrial reliability standards.

The IRF7380PBF belongs to Infineon's HEXFET^® Power MOSFET product line, engineered specifically for high-efficiency, high-frequency power conversion in telecom, server, and industrial power supplies where low switching loss and ruggedness are critical.

FAQ

What is the maximum continuous drain current for each channel at 100°C case temperature?

Each channel supports 2.9 A continuous drain current at T_A = 100°C with V_GS = 10 V, as specified in the Absolute Maximum Ratings table. This value accounts for thermal derating from the 3.6 A rating at 25°C ambient and assumes standard PCB mounting with 1-inch square 2-oz copper.

Does IRF7380PBF support gate drive from 3.3 V logic controllers?

No-its gate threshold voltage (V_GS(th)) ranges from 2.0 V to 4.0 V, and R_DS(on) is only guaranteed at V_GS = 10 V. Driving with 3.3 V may result in incomplete turn-on and excessive conduction loss; a level-shifted or boosted gate drive is required for reliable operation.

How is the effective output capacitance (C_{oss_eff}) measured and why does it matter?

C_{oss_eff} = 140 pF is derived from the energy required to charge C_oss during V_DS rise from 0 to 64 V (80% of 80 V), normalized to a fixed capacitance. It directly determines turn-off switching loss (E_off ≈ ½ × C_{oss_eff} × V_DS² × f_SW) and is essential for accurate loss budgeting in hard-switched topologies.

Can both channels be paralleled to increase current handling?

Yes-both channels are electrically isolated and matched within datasheet tolerances (R_DS(on) variation ≤15%). Paralleling doubles safe operating area and reduces conduction loss, but requires symmetrical PCB layout and individual gate resistors to ensure balanced switching dynamics and prevent current imbalance.