Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Discrete Semiconductor Products > Transistors > FETs, MOSFETs > FETs, MOSFETs

Renesas N0300P-T1B-AT

Name: N0300P-T1B-AT
Brand: Renesas
SKU: N0300P-T1B-AT
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: N0300P-T1B-AT

Manufacturer:: Renesas

Category:: FETs, MOSFETs

Package:: -

Datasheet:: N0300P-T1B-AT.pdf

Description:: SIGNAL DEVICE

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:3,000

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

N0300P-T1B-AT from Renesas Electronics is a P-channel enhancement-mode MOSFET designed for low-voltage DC switching applications, featuring 4.5 V gate drive capability, R_DS(on) ≤ 105 mΩ at V_GS = −4.5 V and I_D = −2.0 A, −30 V drain-source breakdown voltage, and SC-96 surface-mount package. It serves as a compact power switch in portable electronics power rails and load switching circuits.

For engineers reviewing the N0300P-T1B-AT datasheet, N0300P-T1B-AT pinout, N0300P-T1B-AT application, or N0300P-T1B-AT equivalent, key selection criteria include verified 4.5 V logic-level drive compatibility, pulsed drain current rating of −18 A, built-in gate protection diode, thermal derating on FR-4 PCB, and Pb-free SC-96 footprint alignment with space-constrained portable designs.

Technical Context

This device operates as a single P-channel MOSFET with enhancement-mode threshold behavior, requiring negative gate-to-source voltage for conduction. Its gate protection diode provides ESD immunity but mandates external overvoltage clamping when exposed to transients exceeding ±20 V.

Switching performance is characterized by 6.5 ns turn-on delay, 4.0 ns rise time, 34 ns turn-off delay, and 12 ns fall time under −10 V gate drive and 6 Ω source resistance, with total gate charge of 8.3 nC enabling efficient driving from microcontroller GPIOs or dedicated gate drivers.

Key Specifications

Parameter	Value and Actual Design Meaning
V_DSS	−30 V: Maximum blocking voltage before avalanche; suitable for 24 V nominal systems with margin.
R_DS(on) @ V_GS = −4.5 V	105 mΩ max: Enables ≤210 mW conduction loss at −2.0 A DC, critical for thermally constrained PCBs.
I_D(DC)	−4.5 A: Continuous drain current rating at T_ch ≤ 150°C with proper board thermal design.
Q_G	8.3 nC: Low gate charge supports fast switching with minimal driver power consumption.
C_iss	345 pF: Input capacitance impacts gate drive loop stability and rise/fall time predictability.
V_GS(off)	−1.0 to −2.5 V: Confirmed threshold range ensures reliable turn-on at −4.5 V while avoiding false triggering near 0 V.
V_F(S-D)	0.95 V @ I_F = 4.5 A: Body diode forward voltage defines reverse-current path losses in H-bridge or flyback configurations.

Pinout & Package

Package: SC-96 (Mini Mold Thin Type), 3-pin surface-mount, dimensions 2.9 mm × 1.9 mm × 0.65 mm, marked "XZ", Pb-free per J-STD-609.

Pin/Terminal	Circuit Role	Design Meaning
1 (Gate)	Control electrode	Accepts −4.5 V to −20 V gate drive; internal protection diode to Source limits ESD susceptibility.
2 (Source)	Reference terminal	Connected to system ground or high-side return; body diode anode; must be routed with low-inductance trace for switching integrity.
3 (Drain)	Power output terminal	Switches negative rail loads; connects to load return path; requires thermal relief pad for 1.25 W dissipation on 50 mm × 50 mm FR-4.

Key Features

Feature	Design Value
4.5 V logic-level drive	Guarantees full enhancement with standard 5 V or 3.3 V microcontroller outputs without level-shifting circuitry.
Built-in gate protection diode	Provides Class 2 HBM ESD robustness (per datasheet note), reducing need for external TVS in low-risk environments.
Low R_DS(on) at low V_GS	105 mΩ max at −4.5 V enables <100 mW conduction loss in battery-powered load switches operating at 2 A.
SC-96 thin-profile package	0.65 mm height supports ultra-thin portable designs; thermal resistance θ_j-a ≈ 100°C/W on specified FR-4 board.
Pb-free construction	Complies with RoHS Directive 2011/65/EU; no lead in external electrodes or mold compound.

Applications

Smartphone Power Management	USB OTG Power Switch
Use Scenario: Enabling/disabling VBUS power to peripheral devices during USB On-The-Go negotiation. IC Role / Device Role / Timing Role: High-side load switch controlling 5 V rail with fast enable/disable response and low quiescent current. Use Value: R_DS(on) ≤ 105 mΩ minimizes voltage drop across switch, preserving USB 2.0 voltage compliance; 4.5 V drive allows direct control from baseband processor GPIO.	Use Scenario: Isolating host-side 5 V supply from accessory-side VBUS during cable insertion/removal events. IC Role / Device Role / Timing Role: Reverse-polarity protected load switch preventing backfeed into host power domain. Use Value: Integrated body diode blocks reverse current flow; −30 V V_DSS withstands transient overshoots up to ±25 V without clamp diodes.
Bluetooth Headset Battery Protection	Wearable Sensor Node Load Control
Use Scenario: Disconnecting Li-ion battery from charging circuit during overvoltage or thermal fault conditions. IC Role / Device Role / Timing Role: Low-leakage (I_DSS ≤ −1 μA) high-side disconnect switch activated by protection IC signal. Use Value: Gate threshold range (−1.0 to −2.5 V) ensures clean turn-off at 0 V control; low I_DSS preserves battery shelf life >1 year.	Use Scenario: Cycling power to MEMS accelerometers and BLE radios in energy-harvesting wearables. IC Role / Device Role / Timing Role: Ultra-low-duty-cycle load switch minimizing average current draw during sleep states. Use Value: 8.3 nC Q_G enables sub-microsecond switching with <100 nJ gate drive energy, reducing wake-up latency and MCU active time.

Smartphone Power Management

USB OTG Power Switch

Use Scenario: Enabling/disabling VBUS power to peripheral devices during USB On-The-Go negotiation.

IC Role / Device Role / Timing Role: High-side load switch controlling 5 V rail with fast enable/disable response and low quiescent current.

Use Value: R_DS(on) ≤ 105 mΩ minimizes voltage drop across switch, preserving USB 2.0 voltage compliance; 4.5 V drive allows direct control from baseband processor GPIO.

Use Scenario: Isolating host-side 5 V supply from accessory-side VBUS during cable insertion/removal events.

IC Role / Device Role / Timing Role: Reverse-polarity protected load switch preventing backfeed into host power domain.

Use Value: Integrated body diode blocks reverse current flow; −30 V V_DSS withstands transient overshoots up to ±25 V without clamp diodes.

Bluetooth Headset Battery Protection

Wearable Sensor Node Load Control

Use Scenario: Disconnecting Li-ion battery from charging circuit during overvoltage or thermal fault conditions.

IC Role / Device Role / Timing Role: Low-leakage (I_DSS ≤ −1 μA) high-side disconnect switch activated by protection IC signal.

Use Value: Gate threshold range (−1.0 to −2.5 V) ensures clean turn-off at 0 V control; low I_DSS preserves battery shelf life >1 year.

Use Scenario: Cycling power to MEMS accelerometers and BLE radios in energy-harvesting wearables.

IC Role / Device Role / Timing Role: Ultra-low-duty-cycle load switch minimizing average current draw during sleep states.

Use Value: 8.3 nC Q_G enables sub-microsecond switching with <100 nJ gate drive energy, reducing wake-up latency and MCU active time.

Equivalent & Alternatives

The following parts are listed as comparable options for similar P-channel MOSFET switching applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si2301DS-T1-BE3	R_DS(on) = 115 mΩ @ −4.5 V; −20 V V_DSS; same SC-70 package but different pinout (G-S-D vs G-D-S).	Limited to ≤16 V systems; higher R_DS(on) increases conduction loss by ~10% at 2 A.	Select only if board layout accommodates reversed Drain/Source pins and system voltage stays below 16 V.
DMN2053LFG-7	R_DS(on) = 85 mΩ @ −4.5 V; −20 V V_DSS; X1-DFN1006-3 package (1.0 mm × 0.6 mm).	Smaller footprint but lower power handling (0.7 W); no built-in gate protection diode.	Prefer for ultra-compact layouts where gate drive includes external ESD protection and voltage stays ≤16 V.

Compared with Si2301DS-T1-BE3 and DMN2053LFG-7, the N0300P-T1B-AT offers superior −30 V blocking capability and integrated gate protection-critical for unregulated input rails and cost-sensitive designs omitting external TVS-while maintaining competitive R_DS(on) at 4.5 V drive.

Availability

N0300P-T1B-AT is available at Aetrix Electronics and suitable for smartphone power management, USB OTG power switching, and wearable sensor node load control requiring stable component supply across production lifecycles.

Supply support for N0300P-T1B-AT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Renesas Electronics Corporation is a Japanese semiconductor manufacturer formed in 2010 through the merger of NEC Electronics and Renesas Technology, specializing in microcontrollers, analog, power, and mixed-signal solutions.

The N0300P series belongs to Renesas' legacy low-voltage power MOSFET product line, engineered specifically for compact, battery-powered consumer electronics requiring logic-level gate drive and minimal board area.

FAQ

What is the maximum continuous drain current rating for N0300P-T1B-AT under standard PCB conditions?

The N0300P-T1B-AT supports −4.5 A continuous drain current (I_D(DC)) when mounted on a 50 mm × 50 mm × 1.6 mm FR-4 board with adequate copper pour. This rating assumes channel temperature remains ≤150°C; derating applies above 25°C ambient per the published thermal curve in the N0300P datasheet D19782EJ1V0DS.

Does N0300P-T1B-AT include ESD protection, and what is its rated level?

Yes, the N0300P-T1B-AT integrates a gate-to-source protection diode explicitly described in the datasheet as serving "as a protector against ESD." While no HBM or CDM level is numerically specified, the diode structure aligns with Renesas' Standard-grade qualification and provides baseline protection-external TVS is still recommended for harsh environments per the datasheet's design note.

Can N0300P-T1B-AT be driven directly from a 3.3 V microcontroller GPIO?

No-N0300P-T1B-AT requires a negative gate-to-source voltage to conduct; a 3.3 V GPIO alone cannot produce the required −4.5 V relative to the Source. It must be used in high-side configuration with gate drive referenced to Source potential, or paired with a charge pump or level shifter to generate sufficient negative V_GS.

What is the safe operating area (SOA) limitation for N0300P-T1B-AT at 100 μs pulse width?

At 100 μs pulse width, the N0300P-T1B-AT SOA is limited by R_DS(on) to approximately −10 A at −10 V V_DS, per the "Forward Bias Safe Operating Area" graph in datasheet D19782EJ1V0DS. Exceeding this boundary risks thermal runaway due to localized heating, even with low duty cycle.

Is N0300P-T1B-AT compliant with RoHS and REACH regulations?

Yes, N0300P-T1B-AT is Pb-free per J-STD-609 and complies with EU RoHS Directive 2011/65/EU, as confirmed in the ordering information section of the official Renesas datasheet D19782EJ1V0DS. Full material declarations and REACH SVHC status are available via Renesas' component compliance portal using the full part number N0300P-T1B-AT.

N0300P-T1B-AT Specifications

Product attributes: Attribute value

Manufacturer:: Renesas

Series:: -

Package/Case:: -

Packaging:: Bulk

Product Status:: Obsolete

FET Type:: -

Technology:: -

Drain to Source Voltage (Vdss):: -

Current - Continuous Drain (Id) @ 25°C:: 4.5A (Tj)

Drive Voltage (Max Rds On, Min Rds On):: -

Rds On (Max) @ Id, Vgs:: -

Vgs(th) (Max) @ Id:: -

Gate Charge (Qg) (Max) @ Vgs:: -

Vgs (Max):: -

Input Capacitance (Ciss) (Max) @ Vds:: -

FET Feature:: -

Power Dissipation (Max):: -

Operating Temperature:: -

Grade:: -

Qualification:: -

Mounting Type:: -

Supplier Device Package:: -

N0300P-T1B-AT FAQ

1.How can I place an order for N0300P-T1B-AT through Aetrix?

Please submit a Request for Quotation (RFQ) for N0300P-T1B-AT on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for N0300P-T1B-AT reliable?

The price and inventory of N0300P-T1B-AT are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for N0300P-T1B-AT is usually 5 days.

3.What payment methods are accepted for N0300P-T1B-AT?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for N0300P-T1B-AT transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for N0300P-T1B-AT?

N0300P-T1B-AT orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your N0300P-T1B-AT order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for N0300P-T1B-AT?

For technical support, including N0300P-T1B-AT datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your N0300P-T1B-AT requirements.

6.How does Aetrix verify that N0300P-T1B-AT is sourced from the original manufacturer or authorized distributors?

All N0300P-T1B-AT products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that N0300P-T1B-AT meets industry standards.

7.What is the process for return or replacement of N0300P-T1B-AT?

All N0300P-T1B-AT units undergo pre-shipment inspection (PSI). If there is an issue with N0300P-T1B-AT, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The N0300P-T1B-AT part is unused and in its original packaging.

Return procedure for N0300P-T1B-AT:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

2026-08-21 What Is an LED Driver? Types, Circuits, Dimming, and Selection

An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…

2026-08-18 Operational Amplifier (Op Amp): Basics, Configurations, Feedback and Applications

Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…