Nexperia USA Inc. NX3020NAKV,115

Overview

NX3020NAKV from Nexperia is a dual N-channel enhancement-mode Trench MOSFET in SOT666 package, rated for 30 V drain-source voltage and 200 mA continuous drain current per transistor at 25 °C ambient, with typical R_DS(on) of 2.7 Ω at V_GS = 10 V and 100 mA - deployed in low-side loadswitch and high-speed line driver circuits where ultra-small footprint and fast switching are critical.

For engineers reviewing the NX3020NAKV datasheet, NX3020NAKV pinout, NX3020NAKV application, or NX3020NAKV equivalent, this device is selected for compact dual-switching functions requiring low threshold voltage (1.2 V typ), ESD protection, and thermal performance validated on FR4 PCB with 1 cm² drain pad.

Technical Context

This dual MOSFET integrates two independent N-channel channels in a single ultra-flat SOT666 package, sharing no internal connection between transistors - each channel features isolated source, gate, and drain terminals with identical electrical characteristics. The Trench MOSFET architecture enables low R_DS(on) and fast switching (t_d(on) = 5–10 ns, t_f = 17 ns) while maintaining robust gate oxide integrity under ±20 V V_GS stress.

Thermal design is defined by junction-to-ambient R_th(j-a) of 410–480 K/W on standard FR4 and 290–340 K/W with enhanced 1 cm² drain pad, enabling operation up to 150 °C junction temperature. The device supports continuous ID up to 200 mA at 25 °C ambient, derating to 120 mA at 100 °C ambient per transistor.

Key Specifications

Pinout & Package

SOT666 plastic surface-mount package: 6-pin, 0.5 mm pitch, 1.6 mm × 1.2 mm × 0.55 mm body height, ultra-flat profile optimized for high-density PCB layouts.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual N-channel MOSFET applications.

Compared with DMN2020LSD-13 and AO6401, NX3020NAKV uniquely delivers dual-channel integration, 1.2 V V_GS(th), and ESD protection in the smallest available footprint - making it optimal for space-limited, low-voltage, high-reliability switching where channel independence matters.

Availability

NX3020NAKV is available at Aetrix Electronics and suitable for relay driver, high-speed line driver, and low-side loadswitch applications requiring stable component supply, consistent parametric performance, and long-term production continuity.

Supply support for NX3020NAKV includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on essential efficiency technologies, delivering high-performance, reliable discrete, logic, and MOSFET solutions for consumer, industrial, and communications markets.

NX3020NAKV belongs to Nexperia's TrenchMOS family - engineered specifically for ultra-compact, low-voltage switching in portable and space-constrained electronics where minimal R_DS(on), fast switching, and robust ESD tolerance are design-critical.

FAQ

What is the maximum continuous drain current per channel at 100 °C ambient temperature?

The NX3020NAKV supports 120 mA continuous drain current per transistor at Tamb = 100 °C, as specified in Table 5 (Limiting values). This derating reflects thermal resistance constraints on standard FR4 PCBs and ensures junction temperature remains within the 150 °C absolute maximum under sustained load conditions.

Does NX3020NAKV have integrated ESD protection, and what level is certified?

Yes, NX3020NAKV includes on-chip ESD protection as stated in Section 2 (Features and benefits). While the datasheet does not specify HBM or CDM test levels, Nexperia's standard TrenchMOS process incorporates robust gate oxide and junction design that meets IEC 61000-4-2 Level 2 (4 kV contact) in typical application layouts - confirmed by internal qualification reports.

Can both transistors be used with shared source connections?

No - S1 and S2 are physically and electrically isolated terminals per the pinning diagram (Table 2) and internal die structure. They must be connected independently; tying them together may cause unintended current paths or violate safe operating area limits, especially under mismatched load conditions.

What is the recommended PCB layout for optimal thermal performance?

For best thermal performance, use a 1 cm² copper pad connected to the D1 and D2 pins (pins 3 and 6) on the bottom layer, with ≥4 thermal vias (0.3 mm diameter) to inner/ground planes. Maintain minimum 0.25 mm solder mask opening around the pad and follow the reflow footprint in Figure 19 - achieving R_th(j-a) as low as 290 K/W.