My Inquiry
My Account
NXP Semiconductors PH9030L,115
- Part No.:
- PH9030L,115
- Manufacturer:
- NXP Semiconductors
- Category:
- FETs, MOSFETs
- Package:
- SC-100, SOT-669
- Datasheet:
-
PH9030L,115.pdf
- Description:
- MOSFET N-CH 30V 63A LFPAK56
- Quantity:
- Payment:
- Shipping:
Inventory:4,022
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
PH9030L,115 from Nexperia is an N-channel TrenchMOS logic-level power MOSFET in LFPAK (SOT669) package, rated for 30 V VDS, 63 A continuous drain current at Tmb = 25 °C, and 7 mΩ RDS(on) at VGS = 10 V and Tj = 25 °C. It serves as a high-efficiency synchronous rectifier or main switch in DC-DC converters and notebook power rails.
For engineers reviewing the PH9030L,115 datasheet, PH9030L,115 pinout, PH9030L,115 application, or PH9030L,115 equivalent, key selection criteria include logic-level gate drive compatibility (VGS(th) typ. 1.7 V), low thermal resistance (Rth(j-mb) = 2 K/W), avalanche ruggedness (53 mJ), and SOT669 mounting-base thermal path for high-power density designs.
Technical Context
This device uses TrenchMOS technology to achieve low RDS(on) and fast switching with QG(tot) = 13.3 nC and QGD = 3.2 nC at VGS = 4.5 V. Its gate threshold voltage (VGS(th) = 1.3–2.0 V at Tj = 25 °C) ensures reliable turn-on with 3.3 V or 5 V logic drivers.
The integrated source-drain diode supports freewheeling in buck converters, with VSD = 0.89 V at IS = 25 A and trr = 43 ns. Thermal design leverages the mounting base (drain-connected) for direct PCB copper thermal coupling, enabling high-current operation without heatsinks in compact layouts.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VDS | 30 V - Maximum drain-source blocking voltage; suitable for 24 V input systems and 12 V output rails. |
| ID (continuous) | 63 A at Tmb = 25 °C - High current capability enabled by low RDS(on) and efficient thermal path to mounting base. |
| RDS(on) | 7 mΩ max at VGS = 10 V, Tj = 25 °C - Enables <1 W conduction loss at 30 A, critical for high-efficiency power stages. |
| QG(tot) | 13.3 nC typ. - Low total gate charge reduces driver power and enables >1 MHz switching in synchronous buck topologies. |
| Rth(j-mb) | 2 K/W - Junction-to-mounting-base thermal resistance allows direct thermal transfer to PCB copper, simplifying thermal management. |
| EAS | 53 mJ non-repetitive avalanche energy - Supports unclamped inductive switching events in SMPS without failure. |
| VGS(th) | 1.3–2.0 V at Tj = 25 °C - Ensures full enhancement with standard 3.3 V microcontroller GPIOs or PWM controllers. |
Pinout & Package
Package: LFPAK (SOT669), plastic single-ended surface-mounted package with exposed mounting base thermally and electrically connected to drain. Dimensions: 5.0 × 3.3 × 1.3 mm (L × W × H); lead pitch 1.27 mm.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 2, 3 | Source (S) | Three parallel source terminals reduce package inductance and improve current sharing in high-di/dt applications. |
| 4 | Gate (G) | Single gate terminal optimized for low-inductance gate loop; compatible with standard gate drivers and layout practices. |
| Mounting base (mb) | Drain (D) | Exposed copper pad electrically tied to drain and thermally coupled to PCB; primary heat dissipation path and current return path. |
Key Features
| Feature | Design Value |
|---|---|
| Logic-level gate drive | VGS(th) ≤ 2.0 V ensures full enhancement with 3.3 V control signals, eliminating need for level-shifting circuitry. |
| TrenchMOS architecture | Delivers 7 mΩ RDS(on) at 10 V drive while maintaining fast switching (tr = 41 ns, tf = 25 ns) and low QGD/QG ratio for reduced Miller effect. |
| LFPAK thermal design | Mounting base provides 2 K/W Rth(j-mb), enabling >40 A continuous current on 2 oz. copper with 4 cm² thermal pad-no heatsink required. |
| Integrated body diode | VSD = 0.89 V at 25 A and trr = 43 ns support efficient synchronous rectification and freewheeling in buck converters. |
| Avalanche-rated | 53 mJ EAS allows safe operation under inductive load switching transients common in DC-DC and motor drive circuits. |
Applications
| DC-DC Converters | Notebook Computers |
|---|---|
|
Use Scenario: Primary high-side switch in 12 V input → 1.2 V/60 A CPU core VRM. IC Role / Device Role / Timing Role: Main synchronous rectifier MOSFET operating at 500 kHz–1 MHz with 3.3 V gate drive from controller IC. Use Value: 7 mΩ RDS(on) and 13.3 nC QG minimize combined conduction and switching losses, achieving >92% efficiency at full load. |
Use Scenario: Battery protection and load switching in 3-cell Li-ion (12.6 V max) portable platforms. IC Role / Device Role / Timing Role: High-current load switch controlling system power rail with logic-level enable from PMIC. Use Value: 63 A rating and 2.0 V VGS(th) allow direct interface with 3.3 V battery management ICs, reducing BOM count and board space. |
| Portable Equipment | Switched-Mode Power Supplies |
|
Use Scenario: Output rectification in 5 V/10 A USB-C PD adapter secondary side. IC Role / Device Role / Timing Role: Synchronous rectifier replacing Schottky diode to reduce forward drop and thermal stress. Use Value: 0.89 V VSD and 43 ns trr cut conduction loss by >40% vs. 40 V Schottky, improving light-load efficiency and thermal margin. |
Use Scenario: Secondary-side switch in isolated 48 V input telecom DC-DC brick (3.3 V/40 A output). IC Role / Device Role / Timing Role: High-current, high-reliability power switch in industrial-grade SMPS with tight thermal constraints. Use Value: 53 mJ avalanche energy and 150 °C Tj rating ensure robustness against line transients and overloads without derating. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar N-channel logic-level MOSFET applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| PSMN2R0-30YL | RDS(on) = 2.0 mΩ @ 10 V (lower), but QG = 22.5 nC (higher); same SOT669 package and 30 V rating. | Better for ultra-high-efficiency, lower-frequency (<300 kHz) applications where conduction loss dominates. | Select PSMN2R0-30YL when minimizing I²R loss is critical and gate drive strength permits higher QG. |
| IPB033N04LG | 40 V rating, TO-263 package, RDS(on) = 3.3 mΩ @ 10 V; not logic-level (VGS(th) = 2.2–3.3 V). | Requires 5 V gate drive; suited for 36 V input industrial supplies where higher voltage margin is needed. | Choose IPB033N04LG only if 40 V VDS is mandatory and 5 V gate drive is available; not logic-level compatible with PH9030L,115. |
Compared with PSMN2R0-30YL and IPB033N04LG, PH9030L,115 offers optimal balance of logic-level drive, 30 V rating, and 7 mΩ RDS(on) for cost-sensitive, space-constrained 12–24 V DC-DC designs requiring no gate boosting or layout redesign.
Availability
PH9030L,115 is available at Aetrix Electronics and suitable for DC-DC converters, notebook computers, and switched-mode power supplies requiring stable component supply, long-term lifecycle support, and consistent parametric performance across production batches.
Supply support for PH9030L,115 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global leader in discrete, logic, and PowerMOS semiconductors, spun off from NXP in 2017 and focused on automotive, industrial, computing, consumer, and wearable markets.
The PH9030L,115 belongs to Nexperia's TrenchMOS logic-level power MOSFET product line, engineered for high-efficiency, high-current switching in compact, thermally constrained power conversion systems.
FAQ
What is the maximum continuous drain current for PH9030L,115 at 100 °C junction temperature?
The PH9030L,115 supports 39 A continuous drain current at Tj = 100 °C and VGS = 10 V, as specified in Table 4 (Limiting Values). This derating reflects thermal limits and ensures reliable operation under sustained high-temperature conditions typical in enclosed power modules.
Does PH9030L,115 have avalanche capability, and what is its rated energy?
Yes, PH9030L,115 is avalanche-rated with a non-repetitive drain-source avalanche energy (EDS(AL)S) of 53 mJ under defined test conditions (VGS = 10 V, Tj(init) = 25 °C, ID = 33 A, Vsup ≤ 30 V, unclamped, tp = 0.08 ms). This rating is confirmed in Table 4 of the datasheet.
What is the gate-source threshold voltage range for PH9030L,115 across temperature?
The PH9030L,115 has a VGS(th) range of 0.8–2.6 V: minimum 0.8 V at Tj = 150 °C, typical 1.7 V at Tj = 25 °C, and maximum 2.6 V at Tj = -55 °C. These values are documented in Table 6 (Characteristics) and Figure 7 of the datasheet.
Is PH9030L,115 compatible with 3.3 V logic-level gate drive?
Yes, PH9030L,115 is explicitly designed as a logic-level FET with VGS(th) max 2.0 V at 25 °C, ensuring full enhancement using standard 3.3 V microcontroller outputs or PWM controllers without external level shifting.
What is the thermal resistance from junction to mounting base for PH9030L,115?
The PH9030L,115 has a thermal resistance Rth(j-mb) of 2 K/W, measured from junction to mounting base under specified test conditions (Figure 4). This value enables direct thermal coupling to PCB copper and is critical for high-current thermal design.
PH9030L,115 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- -
- Package/Case:
- SC-100, SOT-669
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- FET Type:
- N-Channel
- Technology:
- MOSFET (Metal Oxide)
- Drain to Source Voltage (Vdss):
- 30 V
- Current - Continuous Drain (Id) @ 25°C:
- 63A (Tc)
- Drive Voltage (Max Rds On, Min Rds On):
- 4.5V, 10V
- Rds On (Max) @ Id, Vgs:
- 9mOhm @ 25A, 10V
- Vgs(th) (Max) @ Id:
- 2V @ 1mA
- Gate Charge (Qg) (Max) @ Vgs:
- 13.3 nC @ 4.5 V
- Vgs (Max):
- ±20V
- Input Capacitance (Ciss) (Max) @ Vds:
- 1565 pF @ 12 V
- FET Feature:
- -
- Power Dissipation (Max):
- 62.5W (Tc)
- Operating Temperature:
- -55°C ~ 150°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- LFPAK56, Power-SO8
PH9030L,115 FAQ
1.How can I place an order for PH9030L,115 through Aetrix?
Please submit a Request for Quotation (RFQ) for PH9030L,115 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PH9030L,115 reliable?
The price and inventory of PH9030L,115 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PH9030L,115 is usually 5 days.
3.What payment methods are accepted for PH9030L,115?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PH9030L,115 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PH9030L,115?
PH9030L,115 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PH9030L,115 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PH9030L,115?
For technical support, including PH9030L,115 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PH9030L,115 requirements.
6.How does Aetrix verify that PH9030L,115 is sourced from the original manufacturer or authorized distributors?
All PH9030L,115 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PH9030L,115 meets industry standards.
7.What is the process for return or replacement of PH9030L,115?
All PH9030L,115 units undergo pre-shipment inspection (PSI). If there is an issue with PH9030L,115, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PH9030L,115 part is unused and in its original packaging.
Return procedure for PH9030L,115:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
PH9030L,115 Tags
-
BSZ180P03NS3EGATMA1
Infineon Technologies
-
SIRA14DP-T1-GE3
Vishay Siliconix
-
AO4419
Alpha & Omega Semiconductor Inc.
-
SISA14BDN-T1-GE3
Vishay Siliconix
-
PSMN9R5-30YLC,115
Nexperia USA Inc.
-
BUK9Y21-40E,115
Nexperia USA Inc.
-
RTQ035N03HZGTR
Rohm Semiconductor
-
FDMS7680
onsemi
-
RQ3E180BNTB
Rohm Semiconductor
-
STL6N2VH5
STMicroelectronics
-
DMPH4029LFGQ-7
Diodes Incorporated
-
DMT6015LSS-13
Diodes Incorporated
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
