NXP Semiconductors PHB112N06T,118
- Part No.:
- PHB112N06T,118
- Manufacturer:
- NXP Semiconductors
- Category:
- FETs, MOSFETs
- Package:
- TO-263-3, D2PAK (2 Leads + Tab), TO-263AB
- Datasheet:
-
PHB112N06T,118.pdf
- Description:
- MOSFET N-CH 55V 75A D2PAK
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
PHB112N06T from NXP Semiconductors (formerly Philips Semiconductors) is an N-channel enhancement-mode TrenchMOS™ power MOSFET in SOT404 (D2-PAK) package, rated for 55 V VDS, 75 A ID (DC at Tmb = 25 °C), and 8 mΩ RDS(on) at VGS = 10 V and Tj = 25 °C. It delivers high-current switching in high-efficiency SMPS primary-side switches and motor drive half-bridges.
For engineers reviewing the PHB112N06T datasheet, PHB112N06T pinout, PHB112N06T application, or PHB112N06T equivalent, key selection criteria include its 0.75 K/W junction-to-mounting-base thermal resistance, 87 nC total gate charge, avalanche energy rating of 360 mJ, and compatibility with 10 V gate drive in industrial DC-DC converters and UPS systems.
Technical Context
This device uses TrenchMOS™ technology to achieve low on-resistance and fast switching with controlled Miller charge (Qgd = 29 nC). Its gate threshold voltage ranges from 2.0–4.0 V at 25 °C and drops to 1.0–? V at 175 °C, enabling robust turn-on under elevated temperature conditions.
The integrated source-drain diode supports synchronous rectification and freewheeling, with VSD = 0.85–1.2 V at IS = 25 A and reverse recovery time trr = 65 ns under specified dI/dt and bias conditions - critical for minimizing commutation losses in hard-switched topologies.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VDS | 55 V - Maximum blocking voltage in DC or repetitive pulse operation; defines upper limit for bus voltage in 48 V industrial SMPS. |
| RDS(on) | 7.2–8.0 mΩ @ VGS = 10 V, ID = 25 A, Tj = 25 °C - Enables <1.5 W conduction loss at 50 A, supporting high-current, low-voltage output stages. |
| ID (DC) | 75 A @ Tmb = 25 °C - Sustained current capability when mounted on PCB with minimum copper footprint; derates to 52.5 A at Tmb = 100 °C. |
| EAS | 360 mJ - Non-repetitive avalanche energy rating under unclamped inductive load; allows safe operation during transient overcurrent events without external snubbers. |
| Qg(tot) | 87 nC - Total gate charge required for full turn-on; determines driver strength requirement and switching loss trade-off at 100 kHz+ frequencies. |
| Rth(j-mb) | 0.75 K/W - Junction-to-mounting-base thermal resistance; enables >200 W power dissipation with modest heatsink interface (e.g., 1.5 K/W system Rth yields Tj ≈ 120 °C at 150 W). |
| tr/tf | 94–141 ns / 80–112 ns - Rise/fall times under standardized test conditions; supports efficient hard switching up to ~500 kHz with appropriate gate drive. |
Pinout & Package
SOT404 (D2-PAK) package features a single-ended surface-mount outline with three leads: Gate (pin 1), Drain (pin 2, internally connected to mounting base), and Source (pin 3). Pin 2 is not externally accessible - the drain is tied directly to the thermally conductive mounting base, which must be soldered to a large PCB copper area for thermal management.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | Gate (G) | Control terminal; requires ≥10 V for full enhancement; gate-source leakage ≤100 nA ensures low standby power in PWM controllers. |
| 2 | Drain (D) | High-side power node; electrically and thermally connected to mounting base; no external connection possible - must be routed via PCB copper pour. |
| 3 | Source (S) | Power return path and reference for gate drive; also serves as cathode of integrated body diode for freewheeling current. |
| Mounting Base | Drain (D) | Primary thermal path; provides low-inductance, low-resistance drain connection; must be soldered to ≥10 cm² 2-oz copper for rated Ptot. |
Key Features
| Feature | Design Value |
|---|---|
| TrenchMOS™ technology | Enables 7.2 mΩ RDS(on) in D2-PAK, reducing conduction loss by >30% vs. planar MOSFETs of comparable voltage rating. |
| Avalanche ruggedness | Rated for 360 mJ non-repetitive avalanche energy, allowing reliable operation during inductive turn-off transients without external clamping. |
| Low Qgd/Qgs ratio | Miller charge Qgd = 29 nC vs. Qgs = 24 nC supports stable high-speed switching with reduced risk of shoot-through in bridge configurations. |
| Integrated body diode | VSD = 0.85 V typical at 25 A enables efficient freewheeling in buck and half-bridge topologies without discrete diode replacement. |
| Thermal performance | Rth(j-mb) = 0.75 K/W allows >150 W continuous dissipation with standard PCB heatsinking - suitable for compact 1 kW SMPS designs. |
Applications
| Server PSU Primary Switch | Industrial Motor Drive Half-Bridge |
|---|---|
Use Scenario: High-density 1U server power supply operating at 48 V input, delivering 800 W at 12 V output using phase-shifted full-bridge topology. IC Role / Device Role / Timing Role: Primary-side synchronous rectifier switch handling 60 A peak drain current with 100 kHz PWM frequency and zero-voltage switching transitions. Use Value: 8 mΩ RDS(on) limits conduction loss to <2.9 W at 60 A, while 87 nC Qg enables clean 50 ns turn-on with 2 A gate driver - improving overall efficiency to >95.2%. | Use Scenario: 3-phase BLDC motor controller for HVAC compressors, rated for 220 V AC input and 5 kW mechanical output. IC Role / Device Role / Timing Role: Upper-leg power switch in 3-phase inverter leg, operated in six-step commutation with 20 kHz PWM carrier. Use Value: 360 mJ EAS withstands inductive kickback during fault conditions; 0.75 K/W Rth(j-mb) maintains Tj < 135 °C under 45 A RMS load - eliminating need for forced-air cooling. |
| Uninterruptible Power Supply (UPS) Inverter | Telecom DC-DC Brick |
Use Scenario: Online double-conversion UPS with 48 V battery bank and 230 V AC output, requiring bidirectional energy flow and high reliability. IC Role / Device Role / Timing Role: Bidirectional switch in H-bridge inverter stage, conducting both forward and reverse current during battery charging and discharging cycles. Use Value: Integrated source-drain diode with trr = 65 ns and Qr = 0.17 µC minimizes reverse recovery loss during polarity reversal - extending battery runtime by ~3.1% versus discrete diode solutions. | Use Scenario: 48 V to 12 V isolated DC-DC converter module for 5G base station remote radio units, requiring high power density and low EMI. IC Role / Device Role / Timing Role: Primary-side switch in active-clamp forward topology, operating at 350 kHz with tight duty cycle control. Use Value: Low Ciss = 3264–4352 pF and Crss = 389–533 pF reduce capacitive switching loss and improve EMI profile; 24 ns td(on) enables precise timing control for clamp capacitor reset. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar N-channel power MOSFET applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| STP110N55M6 | 55 V VDS, 110 A ID, 5.5 mΩ RDS(on), TO-220FP package, higher gate charge (120 nC) | Higher current rating but larger footprint and slower switching; better for lower-frequency, higher-current UPS inverters | Select when board space permits larger TO-220FP and peak current exceeds 75 A. |
| IRFB4115PBF | 55 V VDS, 115 A ID, 6.5 mΩ RDS(on), TO-220AB package, 105 nC Qg, no published EAS rating | Superior conduction performance but lacks documented avalanche ruggedness; unsuitable for unclamped inductive loads | Prefer only in well-clamped, low-dI/dt applications where avalanche stress is absent. |
Compared with STP110N55M6 and IRFB4115PBF, PHB112N06T offers optimal balance of low RDS(on), moderate gate charge, and verified 360 mJ avalanche capability in surface-mount D2-PAK - making it uniquely suited for compact, high-reliability 48–60 V industrial SMPS where thermal density and transient robustness are critical.
Availability
PHB112N06T is available at Aetrix Electronics and suitable for switched-mode power supplies, motor drives, and uninterruptible power systems requiring stable component supply across multi-year production cycles.
Supply support for PHB112N06T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor company formed from the spin-off of Philips Semiconductors in 2006, specializing in secure connectivity solutions for automotive, industrial, and IoT markets.
The PHB112N06T belongs to NXP's legacy TrenchMOS™ power MOSFET product line, designed specifically for high-efficiency, high-reliability industrial switching applications demanding low on-resistance, fast switching, and robust avalanche performance.
FAQ
What is the maximum continuous drain current rating for PHB112N06T at 100 °C mounting base temperature?
The PHB112N06T supports 52.5 A continuous drain current at Tmb = 100 °C and VGS = 10 V, as specified in Table 3 (Limiting Values). This derating reflects thermal constraints of the SOT404 package and must be validated against actual PCB copper area and ambient conditions. The PHB112N06T datasheet Figure 2 confirms this normalized current derating curve.
Does PHB112N06T have a specified avalanche energy rating, and under what test conditions is it measured?
Yes, PHB112N06T has a non-repetitive avalanche energy rating of 360 mJ, measured under unclamped inductive load conditions: IAS = 60 A, pulse width tp = 0.1 ms, VDD ≤25 V, RGS = 50 Ω, VGS = 5 V, and starting junction temperature Tj = 25 °C (Figure 4). This rating applies only to single-pulse events and does not imply repetitive avalanche capability.
Can PHB112N06T be used with gate drive voltages below 10 V, and what is its gate threshold voltage range?
PHB112N06T can operate with gate drive down to 5 V, but full enhancement requires ≥10 V for rated RDS(on). Its gate-source threshold voltage VGS(th) is 2.0–4.0 V at Tj = 25 °C and 1.0–? V at Tj = 175 °C (Table 5). Operation below 4.5 V risks incomplete turn-on and excessive conduction loss - the PHB112N06T is optimized for 10 V gate drive in production designs.
What is the thermal resistance from junction to mounting base for PHB112N06T, and how does it impact heatsinking requirements?
The PHB112N06T has Rth(j-mb) = 0.75 K/W (Table 4), meaning each watt dissipated raises junction temperature 0.75 °C above mounting base temperature. To maintain Tj ≤150 °C at 150 W dissipation, the mounting base must stay ≤37.5 °C above ambient - achievable with ≥10 cm² of 2-oz copper and minimal thermal interface resistance. This value is specific to the SOT404 package and confirmed in Figure 5.
Is PHB112N06T pin-compatible with PHP112N06T, and what is the key physical difference between them?
No, PHB112N06T and PHP112N06T are not pin-compatible. PHB112N06T uses SOT404 (D2-PAK) packaging with drain internally connected to the mounting base (pin 2 inaccessible), while PHP112N06T uses SOT78 (TO-220AB) with three fully accessible leads and drain connected to the metal tab. Their footprints, thermal paths, and assembly methods differ fundamentally - the PHB112N06T requires surface-mount reflow and PCB copper heatsinking, unlike the through-hole PHP112N06T.
PHB112N06T,118 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- TrenchMOS™
- Package/Case:
- TO-263-3, D2PAK (2 Leads + Tab), TO-263AB
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- FET Type:
- N-Channel
- Technology:
- MOSFET (Metal Oxide)
- Drain to Source Voltage (Vdss):
- 55 V
- Current - Continuous Drain (Id) @ 25°C:
- 75A (Tc)
- Drive Voltage (Max Rds On, Min Rds On):
- 10V
- Rds On (Max) @ Id, Vgs:
- 8mOhm @ 25A, 10V
- Vgs(th) (Max) @ Id:
- 4V @ 1mA
- Gate Charge (Qg) (Max) @ Vgs:
- 87 nC @ 10 V
- Vgs (Max):
- ±20V
- Input Capacitance (Ciss) (Max) @ Vds:
- 4352 pF @ 25 V
- FET Feature:
- -
- Power Dissipation (Max):
- 200W (Tc)
- Operating Temperature:
- -55°C ~ 175°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- D2PAK
PHB112N06T,118 FAQ
1.How can I place an order for PHB112N06T,118 through Aetrix?
Please submit a Request for Quotation (RFQ) for PHB112N06T,118 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PHB112N06T,118 reliable?
The price and inventory of PHB112N06T,118 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PHB112N06T,118 is usually 5 days.
3.What payment methods are accepted for PHB112N06T,118?
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Once your PHB112N06T,118 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PHB112N06T,118?
For technical support, including PHB112N06T,118 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PHB112N06T,118 requirements.
6.How does Aetrix verify that PHB112N06T,118 is sourced from the original manufacturer or authorized distributors?
All PHB112N06T,118 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PHB112N06T,118 meets industry standards.
7.What is the process for return or replacement of PHB112N06T,118?
All PHB112N06T,118 units undergo pre-shipment inspection (PSI). If there is an issue with PHB112N06T,118, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PHB112N06T,118 part is unused and in its original packaging.
Return procedure for PHB112N06T,118:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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