NXP Semiconductors PHD110NQ03LT,118

Overview

PHD110NQ03LT from NXP Semiconductors (formerly Philips) is an N-channel TrenchMOS™ logic-level power MOSFET in SOT428 (D-PAK) package, designed for high-current switching in low-voltage DC-DC converters and SMPS. It delivers R_DS(on) ≤ 4.6 mΩ at V_GS = 10 V, supports 75 A continuous drain current at T_mb = 25 °C, and features a gate threshold voltage of 1–2 V - enabling direct drive from 3.3 V or 5 V logic controllers.

For engineers reviewing the PHD110NQ03LT datasheet, PHD110NQ03LT pinout, PHD110NQ03LT application, or PHD110NQ03LT equivalent, key selection criteria include its logic-level gate drive compatibility, low on-resistance at 5 V gate bias, avalanche ruggedness (185 mJ), thermal resistance to mounting base (1.3 K/W), and suitability for high-efficiency synchronous rectification and primary-side switching in <25 V systems.

Technical Context

This device employs TrenchMOS™ technology to achieve enhanced channel density and reduced specific on-resistance. Its gate threshold voltage range (1–2 V at 25 °C) ensures reliable turn-on with standard logic-level outputs, while the low Q_g(tot) (26.7 nC typical) and Q_gd (8.4 nC) support fast, efficient switching in high-frequency power stages.

The integrated source-drain diode exhibits V_SD = 0.85–1.2 V at I_S = 25 A and t_rr = 43 ns, making it suitable for freewheeling and synchronous rectifier roles. Thermal design is anchored by R_th(j-mb) = 1.3 K/W, requiring direct thermal coupling to a heatsink via the mounting base (pin 2), which is internally connected to the drain.

Key Specifications

Pinout & Package

PHD110NQ03LT uses the SOT428 (D-PAK) plastic surface-mount package with three leads and an exposed mounting base (MB) electrically tied to the drain. Pin 2 is not externally accessible - the MB serves as the primary thermal and electrical connection point for the drain terminal.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar N-channel logic-level power MOSFET applications.

Compared with IRL3803PBF and STP110N3LLH6, PHD110NQ03LT offers optimal balance of logic-level drive, D-PAK thermal performance, and 25 V rating for cost-sensitive, space-constrained 12–24 V power stages - especially where mounting base thermal coupling is essential and 30 V margin is unnecessary.

Availability

PHD110NQ03LT is available at Aetrix Electronics and suitable for DC-DC converters, switched-mode power supplies, and motor drive circuits requiring stable component supply, long-term manufacturability, and proven thermal reliability in high-current surface-mount applications.

Supply support for PHD110NQ03LT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions, automotive processors, and high-performance analog/power devices - formed from the spin-off of Philips Semiconductors in 2006.

The PHD110NQ03LT belongs to NXP's legacy TrenchMOS™ logic-level power MOSFET family, engineered specifically for high-efficiency, high-current switching in low-voltage (<25 V) power conversion systems where thermal management and gate drive simplicity are critical.

FAQ

What is the maximum continuous drain current rating for PHD110NQ03LT?

The PHD110NQ03LT is rated for 75 A continuous drain current at T_mb = 25 °C with proper heatsinking. At T_mb = 100 °C, this derates to 65 A. The actual usable current depends on PCB copper area, heatsink interface, and ambient conditions - always verify junction temperature using R_th(j-mb) = 1.3 K/W and power dissipation calculations in the PHD110NQ03LT datasheet.

Can PHD110NQ03LT be driven directly by a 3.3 V microcontroller GPIO?

Yes - PHD110NQ03LT has a gate threshold voltage V_GS(th) of 1–2 V at 25 °C, and achieves R_DS(on) ≤ 6.2 mΩ even at V_GS = 5 V. While full 75 A performance requires ≥10 V gate drive, it switches reliably at 3.3 V for moderate-current applications (e.g., <20 A), making PHD110NQ03LT suitable for direct MCU control without external level shifters.

What is the function of the mounting base (MB) on PHD110NQ03LT?

The mounting base (MB) on PHD110NQ03LT is electrically connected to the drain (pin 2) and serves as the primary thermal interface. It must be soldered to a large PCB copper pour or external heatsink to dissipate up to 115 W. Unlike standard SOT-223 or SO-8 packages, this MB enables low R_th(j-mb) = 1.3 K/W - a defining feature of the PHD110NQ03LT's thermal architecture.

Does PHD110NQ03LT include avalanche energy rating, and how is it used?

Yes - PHD110NQ03LT is rated for 185 mJ non-repetitive drain-source avalanche energy (E_DS(AL)S) under defined test conditions (I_D = 43 A, V_DD ≤ 15 V). This rating validates its ability to absorb inductive energy during switching transients without failure, supporting robust operation in flyback, forward, and motor drive circuits where voltage spikes occur.

What package type does PHD110NQ03LT use, and is it compatible with standard D-PAK footprints?

PHD110NQ03LT uses the SOT428 package - Philips' designation for the industry-standard D-PAK (JEDEC TO-252). Its mechanical dimensions (e.g., 6.22 mm × 4.57 mm body, 10.4 mm length) match TO-252 specifications, ensuring full compatibility with standard D-PAK land patterns, stencil apertures, and reflow profiles used for PHD110NQ03LT assembly.