NXP Semiconductors PHD3055E,118

Overview

PHD3055E,118 from NXP Semiconductors (formerly Philips) is an N-channel standard-level TrenchMOS™ power MOSFET in SOT428 (D-PAK) package, rated for 60 V drain-source voltage, 10.3 A continuous drain current at T_mb = 25 °C, and 120–150 mΩ R_DS(on) at V_GS = 10 V and I_D = 5.5 A. It serves as a main or synchronous rectifier switch in high-efficiency DC-DC converters and offline SMPS primary-side switching stages.

For engineers reviewing the PHD3055E,118 datasheet, PHD3055E,118 pinout, PHD3055E,118 application, or PHD3055E,118 equivalent, key selection criteria include its 4.5 K/W junction-to-mounting-base thermal resistance, fast 3–10 ns turn-on delay, low 5.8 nC total gate charge, and avalanche ruggedness of 25 mJ under unclamped inductive conditions - all critical for thermally constrained, high-frequency power stage designs.

Technical Context

This device employs TrenchMOS™ planar trench-gate technology to achieve low R_DS(on) while maintaining robust avalanche capability and stable threshold voltage (V_GS(th) = 2–4 V at T_j = 25 °C). Its gate threshold remains functional down to −55 °C and up to 175 °C, with V_GS(th) shifting to 1 V at T_j = 175 °C and 6 V at T_j = −55 °C.

The PHD3055E,118 features a source-drain diode with 1.1–1.5 V forward voltage at I_S = 10 A and 32 ns reverse recovery time, enabling use in freewheeling or synchronous rectification roles. Its dynamic parameters - including 3.2 nC Miller charge, 190–250 pF input capacitance, and 40–50 pF reverse transfer capacitance - support stable operation in hard-switched topologies up to several hundred kHz.

Key Specifications

Pinout & Package

SOT428 (D-PAK) plastic surface-mount package with isolated mounting base connected internally to drain; pin 2 is inaccessible per datasheet note [1]. Mounting base provides low-thermal-resistance path to PCB copper or heatsink.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar N-channel power MOSFET applications.

Compared with STP30NF20 and IRFR3710ZPBF, the PHD3055E,118 offers optimal balance of voltage rating, thermal resistance (4.5 K/W), and avalanche ruggedness (25 mJ) in the compact D-PAK form factor - making it uniquely suited for cost-sensitive, thermally constrained 48 V power stages where reliability under transient overload is essential.

Availability

PHD3055E,118 is available at Aetrix Electronics and suitable for DC-DC converters, switch-mode power supplies, and motor drive half-bridges requiring stable component supply, long-term lifecycle support, and traceable sourcing for industrial and embedded OEM programs.

Supply support for PHD3055E,118 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor leader focused on secure connectivity solutions for automotive, industrial, and IoT applications, with roots in Philips Semiconductors' power device heritage.

The PHD3055E,118 belongs to NXP's legacy TrenchMOS™ standard-level power MOSFET family, designed specifically for high-reliability, medium-power switching in cost-sensitive industrial and telecom power supplies.

FAQ

What is the maximum continuous drain current rating for PHD3055E,118 at 100 °C mounting base temperature?

The PHD3055E,118 supports 7.3 A continuous drain current at T_mb = 100 °C and V_GS = 10 V, as specified in Table 3 (Limiting Values). This derating reflects thermal constraints of the SOT428 package and must be applied when ambient or PCB thermal conditions prevent maintaining T_mb ≤25 °C. Designers should verify actual mounting base temperature using thermal simulation or measurement before finalizing current ratings.

Does PHD3055E,118 have a documented avalanche energy rating, and how is it tested?

Yes, the PHD3055E,118 has a non-repetitive drain-source avalanche energy rating of 25 mJ (E_DS(AL)S), measured under unclamped inductive load conditions: I_D = 3.3 A, t_AL = 0.22 ms, V_DD ≤25 V, R_GS = 50 Ω, V_GS = 10 V, and starting T_j = 25 °C. This value is confirmed in Table 3 and validated per IEC 60134 limiting values methodology - enabling safe use in flyback, boost, and relay-driving applications with inductive kickback.

Can PHD3055E,118 be used in synchronous rectification configurations?

Yes, the PHD3055E,118 is suitable for synchronous rectification due to its low R_DS(on) (120–150 mΩ), fast 32 ns reverse recovery time (t_rr), and 50 nC recovered charge (Q_r). Its source-drain diode forward voltage is 1.1–1.5 V at I_S = 10 A, allowing efficient replacement of Schottky diodes in secondary-side rectification of DC-DC converters - provided gate timing avoids shoot-through and accounts for V_GS(th) variation across temperature.

What is the thermal resistance from junction to mounting base (R_th(j-mb)) for PHD3055E,118, and how does it impact PCB layout?

The PHD3055E,118 has a maximum R_th(j-mb) of 4.5 K/W, as stated in Table 4. This low value requires direct thermal coupling between the mounting base (pin 2, internal drain connection) and a large copper pour or external heatsink. PCB layout must allocate ≥250 mm² of 2-oz copper connected to the mounting pad with ≥4 thermal vias (0.3 mm diameter, spaced ≤1.5 mm apart) to realize this thermal performance - otherwise, junction temperature will exceed 175 °C under full load.

Is PHD3055E,118 pin-compatible with other D-PAK MOSFETs such as the IRFR3710ZPBF?

No, PHD3055E,118 is not pin-compatible with IRFR3710ZPBF despite sharing the SOT428 (D-PAK) outline. While both use 3-lead D-PAK packages, PHD3055E,118 has pin 2 internally connected to drain and inaccessible externally - whereas IRFR3710ZPBF exposes all three pins (G-D-S) with pin 2 as drain. Substitution requires PCB layout revision to accommodate the different pin access configuration and thermal pad routing.