Nexperia USA Inc. PHD38N02LT,118
- Part No.:
- PHD38N02LT,118
- Manufacturer:
- Nexperia USA Inc.
- Category:
- FETs, MOSFETs
- Package:
- TO-252-3, DPAK (2 Leads + Tab), SC-63
- Datasheet:
-
PHD38N02LT,118.pdf
- Description:
- MOSFET N-CH 20V 44.7A DPAK
- Quantity:
- Payment:

- Shipping:

Inventory:8,567
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
PHD38N02LT from NXP Semiconductors is a logic-level N-channel TrenchMOS FET in DPAK (SOT428) package, designed for low-voltage switching with 2.5 V gate drive capability, 20 V drain-source rating, 44.7 A continuous drain current at Tmb = 25 °C, and 13.5 mΩ typical RDS(on) at VGS = 5 V - used in DDR memory linear regulators.
For engineers reviewing the PHD38N02LT datasheet, PHD38N02LT pinout, PHD38N02LT application, or PHD38N02LT equivalent, this device is selected for high-current, low-VGS power switching where thermal performance on PCB-mounted base and fast turn-on/turn-off timing are critical.
Technical Context
This FET employs TrenchMOS technology to achieve low RDS(on) and enhanced gate charge efficiency, supporting logic-level drive down to 2.5 V while maintaining robust safe operating area up to 179 A peak pulsed current. Its mounting base (pin 2) is internally connected to drain and serves as primary thermal path.
The device features a source-drain diode with 0.98 V forward voltage at 25 A and exhibits stable threshold voltage (VGS(th) = 0.5–1.5 V) across −55 °C to +175 °C junction temperature, enabling reliable operation in thermally demanding DC-DC and load-switching applications.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VDS | 20 V maximum - defines absolute upper limit for drain-source blocking in DDR supply rails and low-voltage load switches. |
| ID (continuous) | 44.7 A at Tmb = 25 °C - supports high-current linear regulation without external heatsink under moderate PCB copper area. |
| RDS(on) | 13.5 mΩ typical at VGS = 5 V, Tj = 25 °C - enables <1.1 W conduction loss at 25 A, critical for thermal budget in compact DDR modules. |
| QG(tot) | 15.1 nC - determines gate driver strength requirement; compatible with standard logic-level drivers (e.g., microcontroller GPIO or dedicated gate buffers). |
| Rth(j-mb) | 2.6 K/W - quantifies thermal resistance from junction to mounting base, enabling accurate PCB thermal design using copper pour under the DPAK base. |
| VGS(th) | 0.5–1.5 V at Tj = 25 °C - ensures full enhancement with 2.5 V logic signals, eliminating need for level-shifting in 3.3 V or lower control systems. |
Pinout & Package
PHD38N02LT uses the SOT428 (DPAK) plastic surface-mount package with three leads and one cropped lead. The mounting base (mb) is electrically connected to the drain and serves as the primary thermal interface to the PCB.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (G) | Gate | Control terminal; accepts logic-level input (2.5–12 V); requires ≤15.1 nC charge for full turn-on. |
| 2 (D / mb) | Drain & Mounting Base | Main power input; electrically tied to exposed metal pad; must be soldered to large PCB copper area for thermal management. |
| 3 (S) | Source | Power return path; referenced to system ground in low-side switch configuration; carries full load current. |
Key Features
| Feature | Design Value |
|---|---|
| Logic-level gate drive | Operates fully enhanced at VGS ≥ 2.5 V - eliminates gate driver ICs in 3.3 V/2.5 V control domains. |
| TrenchMOS architecture | Delivers 13.5 mΩ RDS(on) with minimal gate charge - improves switching efficiency and reduces driver losses. |
| Drain-connected mounting base | 2.6 K/W Rth(j-mb) enables >50 W power dissipation with proper PCB copper - avoids discrete heatsinks in space-constrained DDR modules. |
| Robust SOA | 179 A peak drain current (10 µs pulse) supports inrush current handling in hot-swap and load-switch applications. |
Applications
| DDR Memory Linear Regulator | Hot-Swap Load Switch |
|---|---|
Use Scenario: Provides precise, low-noise voltage regulation for DDR2/DDR3 memory termination supplies (VTT), requiring fast transient response and minimal dropout. IC Role / Device Role / Timing Role: Low-side pass element in linear regulator topology; conducts continuously during memory operation. Use Value: 13.5 mΩ RDS(on) limits dropout to <0.3 V at 20 A, preserving tight VTT tolerance while dissipating <1.2 W under full load. |
Use Scenario: Enables controlled power-up of peripheral modules (e.g., USB add-on cards, FPGA mezzanines) without inrush-induced rail collapse. IC Role / Device Role / Timing Role: High-current, low-VGS power switch placed between main rail and module input; driven by enable signal. Use Value: 179 A peak current rating safely handles 100 ms inrush surges; 2.5 V gate compatibility allows direct MCU GPIO control. |
| Industrial 24 V DC Load Switch | Automotive Body Control Module (BCM) Output |
Use Scenario: Replaces electromechanical relays in programmable 24 V industrial I/O modules for solenoid, valve, and lamp loads. IC Role / Device Role / Timing Role: Low-side switching element; handles resistive and inductive loads with integrated freewheeling path via body diode. Use Value: 0.98 V VSD at 25 A enables efficient inductive flyback clamping; 20 V VDS rating suits 24 V nominal systems with 30 V transients. |
Use Scenario: Drives interior lighting, seat motors, and window lifters in automotive BCMs where space and thermal constraints limit discrete solutions. IC Role / Device Role / Timing Role: High-side or low-side power switch; operated under PWM or on/off control per vehicle ECU command. Use Value: −55 °C to +175 °C operating range meets AEC-Q101 ambient requirements; 1.5 V max VGS(th) ensures turn-on with 3.3 V CAN/LIN controller outputs. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar N-channel logic-level power MOSFET applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| STL32N20L | RDS(on) = 15 mΩ @ VGS = 4.5 V; 20 V VDS; same DPAK package but higher gate charge (22 nC). | Slightly higher conduction loss and slower switching due to larger QG; less suitable for high-frequency PWM. | Prefer PHD38N02LT when minimizing gate drive burden or optimizing thermal performance on limited PCB copper. |
| IRLML6344TRPBF | RDS(on) = 22 mΩ @ VGS = 2.5 V; 20 V VDS; SOT-23 package (lower power, no mounting base). | Not thermally scalable beyond ~3 A; lacks drain-connected thermal pad - unsuitable for >10 W dissipation. | Choose PHD38N02LT for applications exceeding 10 W power handling or requiring PCB-level thermal management. |
Compared with STL32N20L and IRLML6344TRPBF, PHD38N02LT delivers superior thermal performance via its DPAK mounting base and lowest gate charge among 20 V logic-level FETs, making it optimal for high-current linear regulation and robust load switching where board-level heat spreading is essential.
Availability
PHD38N02LT is available at Aetrix Electronics and suitable for DDR memory linear regulators, hot-swap load switches, and industrial 24 V DC load switching requiring stable component supply and long-term manufacturability.
Supply support for PHD38N02LT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and consumer applications.
PHD38N02LT belongs to NXP's TrenchMOS logic-level power MOSFET product line, engineered for high-efficiency, low-voltage switching in space-constrained power management systems where gate drive simplicity and thermal reliability are critical.
FAQ
Is PHD38N02LT suitable for high-frequency PWM applications?
No - PHD38N02LT is optimized for DC and low-frequency switching (≤100 kHz) due to its 15.1 nC total gate charge and 30 ns turn-off delay. For high-frequency SMPS, devices with lower QG and faster tf/tr (e.g., <5 ns) are recommended. Its strength lies in linear regulation and load switching where efficiency stems from ultra-low RDS(on), not switching speed.
Can PHD38N02LT be used in high-side switch configurations?
Yes, but only with appropriate gate drive circuitry that provides VGS ≥ 2.5 V relative to the source node. Since it is an N-channel device, high-side use requires a bootstrap or isolated gate driver to elevate the gate voltage above the drain rail. It is more commonly deployed as a low-side switch for simplicity and thermal efficiency.
What is the significance of the "cropped lead" in the DPAK package?
The cropped lead (lead 2) in SOT428 corresponds to the drain connection and is internally bonded to the mounting base. This design maximizes thermal contact area between the die and PCB copper while minimizing parasitic inductance. The cropped geometry prevents accidental shorting during assembly and ensures mechanical stability when soldered to a thermal pad.
Does PHD38N02LT have avalanche ruggedness rated in the datasheet?
No - the datasheet does not specify single-pulse or repetitive avalanche energy (EAS). It is not characterized or guaranteed for unclamped inductive switching. Designers must ensure external protection (e.g., TVS, snubbers) or operate within the SOA curve (Figure 3) to avoid destructive failure during inductive load switching.
PHD38N02LT,118 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- TrenchMOS™
- Package/Case:
- TO-252-3, DPAK (2 Leads + Tab), SC-63
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- FET Type:
- N-Channel
- Technology:
- MOSFET (Metal Oxide)
- Drain to Source Voltage (Vdss):
- 20 V
- Current - Continuous Drain (Id) @ 25°C:
- 44.7A (Tc)
- Drive Voltage (Max Rds On, Min Rds On):
- 5V
- Rds On (Max) @ Id, Vgs:
- 16mOhm @ 25A, 5V
- Vgs(th) (Max) @ Id:
- 1.5V @ 250µA
- Gate Charge (Qg) (Max) @ Vgs:
- 15.1 nC @ 5 V
- Vgs (Max):
- ±12V
- Input Capacitance (Ciss) (Max) @ Vds:
- 800 pF @ 20 V
- FET Feature:
- -
- Power Dissipation (Max):
- 57.6W (Tc)
- Operating Temperature:
- -55°C ~ 175°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- DPAK
PHD38N02LT,118 FAQ
1.How can I place an order for PHD38N02LT,118 through Aetrix?
Please submit a Request for Quotation (RFQ) for PHD38N02LT,118 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PHD38N02LT,118 reliable?
The price and inventory of PHD38N02LT,118 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PHD38N02LT,118 is usually 5 days.
3.What payment methods are accepted for PHD38N02LT,118?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PHD38N02LT,118 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PHD38N02LT,118?
PHD38N02LT,118 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PHD38N02LT,118 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PHD38N02LT,118?
For technical support, including PHD38N02LT,118 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PHD38N02LT,118 requirements.
6.How does Aetrix verify that PHD38N02LT,118 is sourced from the original manufacturer or authorized distributors?
All PHD38N02LT,118 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PHD38N02LT,118 meets industry standards.
7.What is the process for return or replacement of PHD38N02LT,118?
All PHD38N02LT,118 units undergo pre-shipment inspection (PSI). If there is an issue with PHD38N02LT,118, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PHD38N02LT,118 part is unused and in its original packaging.
Return procedure for PHD38N02LT,118:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
PHD38N02LT,118 Tags

-
BSZ180P03NS3EGATMA1
Infineon Technologies

-
SIRA14DP-T1-GE3
Vishay Siliconix

-
AO4419
Alpha & Omega Semiconductor Inc.

-
SISA14BDN-T1-GE3
Vishay Siliconix

-
PSMN9R5-30YLC,115
Nexperia USA Inc.

-
BUK9Y21-40E,115
Nexperia USA Inc.

-
RTQ035N03HZGTR
Rohm Semiconductor

-
FDMS7680
onsemi

-
RQ3E180BNTB
Rohm Semiconductor

-
STL6N2VH5
STMicroelectronics

-
DMPH4029LFGQ-7
Diodes Incorporated

-
DMT6015LSS-13
Diodes Incorporated
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

