Nexperia USA Inc. PHD97NQ03LT,118
- Part No.:
- PHD97NQ03LT,118
- Manufacturer:
- Nexperia USA Inc.
- Category:
- FETs, MOSFETs
- Package:
- TO-252-3, DPAK (2 Leads + Tab), SC-63
- Datasheet:
-
PHD97NQ03LT,118.pdf
- Description:
- MOSFET N-CH 25V 75A DPAK
- Quantity:
- Payment:

- Shipping:

Inventory:3,973
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Product details
Overview
PHD97NQ03LT from Nexperia is a logic-level N-channel TrenchMOS power FET in DPAK (SOT428) package, rated for 25 V VDS, 75 A continuous drain current at Tmb = 25 °C, and 5.3 mΩ RDS(on) at VGS = 10 V and Tj = 25 °C. It serves as a high-efficiency synchronous rectifier or main switch in DC-DC converters on computing motherboards.
For engineers reviewing the PHD97NQ03LT datasheet, PHD97NQ03LT pinout, PHD97NQ03LT application, or PHD97NQ03LT equivalent, key selection criteria include its 1.7 V typical gate threshold voltage enabling direct 3.3 V/5 V logic drive, low QGD (1.9 nC) for fast switching in high-frequency SMPS, and mounting-base thermal path supporting 107 W Ptot with Rth(j-mb) = 1.4 K/W.
Technical Context
This device uses TrenchMOS technology to achieve low RDS(on) and fast dynamic performance. Its logic-level VGS(th) (1.3–2.15 V) ensures full enhancement with standard microcontroller GPIOs, while its 1.9 nC QGD and 33 ns tr support operation above 500 kHz in buck converters.
The integrated source-drain diode exhibits 0.87 V typical VSD at 25 A and 38 ns trr, enabling efficient body-diode conduction during dead-time intervals. Thermal design leverages the exposed mounting base (connected to drain), delivering 1.4 K/W junction-to-mounting-base resistance under PCB-mounted conditions.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VDS | 25 V - Maximum blocking voltage compatible with 12 V and 19 V input rails in point-of-load converters. |
| RDS(on) | 5.3 mΩ @ VGS = 10 V, Tj = 25 °C - Enables <1.3 W conduction loss at 25 A, critical for thermally constrained motherboard layouts. |
| QGD | 1.9 nC - Low gate-drain charge minimizes Miller-induced switching delay and improves hard-switching efficiency above 300 kHz. |
| tr/tf | 33 ns / 12 ns - Fast edge rates reduce transition losses and EMI generation in high-frequency synchronous rectifiers. |
| VGS(th) | 1.7 V typ @ Tj = 25 °C - Ensures reliable turn-on with 3.3 V logic drivers without level-shifting circuitry. |
| Rth(j-mb) | 1.4 K/W - Direct thermal path to PCB copper enables high-power operation without heatsinks in space-constrained applications. |
| EAS | 60 mJ - Unclamped avalanche energy rating supports robustness against inductive switching transients in non-isolated topologies. |
Pinout & Package
PHD97NQ03LT is housed in a plastic DPAK (SOT428/SC-63) surface-mount package with an exposed mounting base electrically connected to the drain terminal. The package features three leads (one cropped), optimized for high-current PCB thermal management.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (G) | Gate | Control electrode; accepts logic-level drive (VGS(th) = 1.7 V typ); requires <12 nC total gate charge for full switching. |
| 2 (D) + mb | Drain + Mounting Base | Main high-side current path; mounting base is electrically tied to drain and serves as primary thermal interface to PCB copper pour. |
| 3 (S) | Source | Power return node; referenced for gate drive; forms low-impedance path for synchronous rectifier current flow. |
Key Features
| Feature | Design Value |
|---|---|
| Logic-level gate drive compatibility | 1.7 V typical VGS(th) allows direct interfacing with 3.3 V/5 V microcontrollers and PWM controllers without gate drivers. |
| Low RDS(on) with temperature stability | 5.3 mΩ @ 25 °C rising to 10.1 mΩ @ 175 °C - maintains efficiency across industrial temperature range in VRMs. |
| Fast switching with low QGD | 1.9 nC gate-drain charge reduces Miller plateau duration, enabling clean turn-off in high-dV/dt synchronous buck stages. |
| Robust avalanche capability | 60 mJ unclamped avalanche energy - withstands transient overvoltage events during load dump or inductive kickback. |
| Lead-free and RoHS-compliant packaging | SOT428 package meets JEDEC J-STD-020 moisture sensitivity level 1 and IPC/JEDEC J-STD-033 handling requirements. |
Applications
| Computer Motherboard DC-DC Converters | Server VRM High-Side Switch |
|---|---|
Use Scenario: Primary switch in multiphase buck converters supplying CPU core voltage (e.g., 0.8–1.3 V @ >100 A). IC Role / Device Role / Timing Role: High-side power switch operating at 300–600 kHz with synchronous rectification. Use Value: 5.3 mΩ RDS(on) and 33 ns rise time minimize conduction and switching losses, improving converter efficiency by ≥1.2% at full load. |
Use Scenario: High-current phase-leg switch in server voltage regulator modules powering Xeon or EPYC processors. IC Role / Device Role / Timing Role: Main switching FET in interleaved buck topology with active current balancing. Use Value: 107 W Ptot and 1.4 K/W Rth(j-mb) enable sustained 75 A operation on 2-oz copper PCBs without auxiliary cooling. |
| Industrial SMPS Primary Switch | Telecom DC-DC Intermediate Bus Converter |
Use Scenario: Main switch in 24 V input, 12 V output offline SMPS for factory automation controllers. IC Role / Device Role / Timing Role: Hard-switched MOSFET in flyback or forward converter operating up to 250 kHz. Use Value: 25 V VDS rating and 60 mJ avalanche energy ensure reliability during line surges and transformer leakage spikes. |
Use Scenario: Step-down converter feeding 5 V/3.3 V rails from 48 V telecom intermediate bus in base station power systems. IC Role / Device Role / Timing Role: High-efficiency synchronous rectifier in non-isolated buck stage. Use Value: 0.87 V source-drain diode forward voltage and 38 ns reverse recovery time reduce body-diode conduction losses during dead time. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar N-channel logic-level power FET applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| IRL3803PBF | RDS(on) = 6.0 mΩ @ 10 V, QGD = 2.4 nC, TO-220 package (no mounting base thermal path) | Lacks integrated thermal base; requires external heatsink for >40 A operation; higher switching loss at >400 kHz | Prefer PHD97NQ03LT for surface-mount, high-density, high-frequency designs where PCB thermal management is prioritized. |
| FDMS86102 | RDS(on) = 4.8 mΩ @ 10 V, QGD = 1.7 nC, PowerTrench® 5x6 mm PQFN with dual-side cooling | Lower RDS(on) but requires more complex layout; no drain-connected thermal pad - thermal path differs significantly | Choose FDMS86102 only when board stack-up allows double-sided thermal vias and footprint change is acceptable. |
Compared with IRL3803PBF and FDMS86102, PHD97NQ03LT uniquely balances ultra-low QGD, logic-level drive, and DPAK's proven mounting-base thermal interface - making it optimal for cost-sensitive, high-volume motherboard and VRM designs requiring ≤25 V blocking and ≥70 A DC current.
Availability
PHD97NQ03LT is available at Aetrix Electronics and suitable for computer motherboard DC-DC converters, industrial switched-mode power supplies, and telecom intermediate bus converters requiring stable component supply and long-term production continuity.
Supply support for PHD97NQ03LT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on high-volume, high-reliability discrete, logic, and MOSFET solutions, with manufacturing rooted in process control and automotive-grade quality systems.
PHD97NQ03LT belongs to Nexperia's TrenchMOS logic-level power FET product line, engineered specifically for high-efficiency, high-frequency DC-DC conversion in computing and communications infrastructure where thermal density and gate-drive simplicity are critical.
FAQ
What is the maximum continuous drain current for PHD97NQ03LT at 100 °C mounting base temperature?
The datasheet specifies 69 A continuous drain current at Tmb = 100 °C and VGS = 10 V, derived from derating curves in Figure 1. This reflects real-world thermal limits when mounted on standard 2-layer 1-oz copper PCBs without forced airflow.
Does PHD97NQ03LT have an integrated Schottky body diode?
No - it uses a standard silicon body diode inherent to the MOSFET structure. Its VSD is 0.87 V at 25 A and 25 °C, with 38 ns reverse recovery time (trr) and 14 nC recovered charge (Qr), as measured per Figure 12 and Table 6.
Can PHD97NQ03LT be used in avalanche mode for circuit protection?
Yes - it is rated for 60 mJ unclamped avalanche energy (EAS) at Tj(init) = 25 °C, ID = 35 A, and Vsup ≤25 V. This capability is validated per JEDEC JESD24-1 and supports limited transient clamping in non-isolated topologies.
Is the mounting base electrically isolated from the drain terminal?
No - the mounting base (mb) is internally connected to the drain (Pin 2), as confirmed in Table 2 ("mb: mounting base; connected to drain") and Figure 13 package outline. This configuration mandates proper PCB isolation of the drain copper pour from other nets.
PHD97NQ03LT,118 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- TrenchMOS™
- Package/Case:
- TO-252-3, DPAK (2 Leads + Tab), SC-63
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- FET Type:
- N-Channel
- Technology:
- MOSFET (Metal Oxide)
- Drain to Source Voltage (Vdss):
- 25 V
- Current - Continuous Drain (Id) @ 25°C:
- 75A (Tc)
- Drive Voltage (Max Rds On, Min Rds On):
- 4.5V, 10V
- Rds On (Max) @ Id, Vgs:
- 6.3mOhm @ 25A, 10V
- Vgs(th) (Max) @ Id:
- 2.15V @ 1mA
- Gate Charge (Qg) (Max) @ Vgs:
- 11.7 nC @ 4.5 V
- Vgs (Max):
- ±20V
- Input Capacitance (Ciss) (Max) @ Vds:
- 1570 pF @ 12 V
- FET Feature:
- -
- Power Dissipation (Max):
- 107W (Tc)
- Operating Temperature:
- -55°C ~ 175°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- DPAK
PHD97NQ03LT,118 FAQ
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6.How does Aetrix verify that PHD97NQ03LT,118 is sourced from the original manufacturer or authorized distributors?
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7.What is the process for return or replacement of PHD97NQ03LT,118?
All PHD97NQ03LT,118 units undergo pre-shipment inspection (PSI). If there is an issue with PHD97NQ03LT,118, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PHD97NQ03LT,118 part is unused and in its original packaging.
Return procedure for PHD97NQ03LT,118:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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