Nexperia USA Inc. PMCPB5530X,115

Overview

PMCPB5530X,115 from Nexperia is a complementary N/P-channel Trench MOSFET pair in a DFN2020-6 (SOT1118) package, designed for bidirectional power switching in space-constrained portable systems. It delivers 20 V drain-source voltage rating, 26 mΩ N-channel and 55 mΩ P-channel R_DS(on) at 4.5 V gate drive, and supports 5.3 A N-channel / −4.5 A P-channel continuous drain current - enabling compact charging switches and DC-DC converter high-side/low-side control.

For engineers reviewing the PMCPB5530X,115 datasheet, PMCPB5530X,115 pinout, PMCPB5530X,115 application, or PMCPB5530X,115 equivalent, this dual-channel discrete FET offers verified thermal performance via exposed drain pad, fast switching (4 ns turn-on delay), and validated operation across −55 °C to 150 °C junction temperature range in battery-powered power management circuits.

Technical Context

This device integrates two enhancement-mode MOSFETs - an N-channel (TR1) with V_GS(th) = 0.65 V typ and a P-channel (TR2) with V_GS(th) = −0.65 V typ - sharing a monolithic die in a thermally enhanced leadless package. Both channels support ±12 V gate-source voltage and exhibit matched dynamic characteristics: Q_G(tot) of 14.4 nC (N) and 8.1 nC (P), with C_iss values of 660 pF and 785 pF respectively.

The DFN2020-6 footprint features an exposed drain pad (pins 3 and 6) for low R_th(j-sp) (10–15 K/W), enabling efficient heat transfer to PCB copper. Pin configuration separates source/gate/drain terminals per channel without internal connection, supporting independent gate control for synchronous buck or H-bridge topologies.

Key Specifications

Pinout & Package

DFN2020-6 (SOT1118) is a 2.0 mm × 2.0 mm × 0.65 mm leadless plastic package with an exposed drain pad for thermal conduction. Six terminals are arranged in a single row with no leads; pins 3 and 6 connect to the common drain pad (TR1 D1 and TR2 D2).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar complementary MOSFET applications.

Compared with DMC3025LSD-13 and SI3588DV-T1-GE3, PMCPB5530X,115 provides optimal balance of ultra-compact size, low R_DS(on), and fast switching - making it preferred for high-frequency, space-critical portable power stages where thermal performance and layout simplicity are prioritized.

Availability

PMCPB5530X,115 is available at Aetrix Electronics and suitable for charging switches, DC-DC converters, and small BLDC motor drives requiring stable component supply and long-term manufacturability in consumer electronics production.

Supply support for PMCPB5530X,115 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on essential semiconductors, delivering high-performance, reliable discrete, logic, and MOSFET solutions for automotive, industrial, and consumer markets.

PMCPB5530X,115 belongs to Nexperia's TrenchMOS complementary FET product line, engineered specifically for high-efficiency, miniaturized power management in battery-powered portable electronics.

FAQ

What is the maximum continuous drain current for each channel at 100 °C ambient?

At T_amb = 100 °C with standard FR4 mounting (single-sided copper, 6 cm² drain pad), the N-channel supports 2.6 A continuous drain current and the P-channel supports −2.2 A. These values derive from derating curves in Table 5 and Fig 2/18, reflecting thermal limits under sustained operation.

Can PMCPB5530X,115 be used in a synchronous boost converter?

No - the device lacks integrated body diode optimization for reverse recovery in boost topologies. Its P-channel is rated for −20 V V_DS, limiting use to step-down or bidirectional switching. For boost, a dedicated N-channel+N-channel or logic-level P-channel with faster V_SD recovery is required.

Is the exposed drain pad electrically connected between TR1 and TR2?

Yes - pins 3 (D2) and 6 (D1) are internally connected to the same exposed copper pad, forming a common drain node. This allows shared thermal sinking but prohibits independent drain biasing; both channels must operate with drains at identical potential.

What is the gate threshold voltage variation over temperature?

V_GS(th) decreases linearly with junction temperature: N-channel drops from 0.65 V at 25 °C to ~0.45 V at 150 °C (Fig 11); P-channel shifts from −0.65 V to ~−0.45 V (Fig 22). This negative tempco ensures stable turn-on margin across operating range without external compensation.