Nexperia USA Inc. PMDPB30XNAX

Overview

PMDPB30XNAX from Nexperia is a dual N-channel Trench MOSFET in a DFN2020-6 (SOT1118) package, rated for 20 V drain-source voltage, 4.5 A continuous drain current per transistor at 25 °C, and 26 mΩ typical R_DS(on) at V_GS = 4.5 V - designed for low-side load switching and DC–DC conversion in space-constrained automotive and industrial power stages.

For engineers reviewing the PMDPB30XNAX datasheet, PMDPB30XNAX pinout, PMDPB30XNAX application, or PMDPB30XNAX equivalent, key selection criteria include its AEC-Q101 qualification, ultra-thin 2 × 2 × 0.65 mm thermal-enhanced package, exposed drain pad for 11 K/W junction-to-solder-point thermal resistance, and fast switching with 6.6 nC total gate charge and 2.3 ns rise time.

Technical Context

This dual discrete MOSFET integrates two independent N-channel enhancement-mode transistors sharing no internal connection - each with separate gate, source, and drain terminals. Its Trench MOSFET architecture delivers low threshold voltage (0.4–0.9 V), high transconductance (8 S typ), and robust avalanche ruggedness (4.5 mJ per transistor).

Thermal performance is optimized via an exposed drain pad thermally coupled to PCB copper; under standard FR4 mounting (6 cm² drain pad), it achieves 1.6 W total power dissipation and supports 12 A pulsed drain current. Gate drive compatibility includes logic-level operation down to 1.8 V with R_DS(on) ≤ 80 mΩ.

Key Specifications

Pinout & Package

DFN2020-6 (SOT1118) is a leadless, ultra-thin surface-mount package with an exposed drain pad on the bottom side for enhanced thermal conduction. Dimensions: 2.0 mm × 2.0 mm × 0.65 mm body height; 0.65 mm pitch; six terminals arranged in a single row with terminal 1 index marked.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual N-channel MOSFET applications.

Compared with DMN2020LSD-13 and SI2302DDS-T1-GE3, PMDPB30XNAX uniquely combines AEC-Q101 qualification, dual independent channels in 4 mm², and 11 K/W thermal resistance - making it the only option for thermally dense automotive DC–DC and industrial load switching where reliability and footprint are co-constrained.

Availability

PMDPB30XNAX is available at Aetrix Electronics and suitable for automotive DC–DC converters, industrial low-side load switches, and high-speed line drivers requiring stable component supply across production lifecycles.

Supply support for PMDPB30XNAX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on essential semiconductors - delivering high-performance, reliable components for automotive, industrial, mobile, and computing markets.

PMDPB30XNAX belongs to Nexperia's TrenchMOS portfolio, engineered specifically for high-efficiency, space-constrained power switching in automotive and industrial systems where thermal density and AEC-Q101 compliance are mandatory.

FAQ

Is PMDPB30XNAX pin-compatible with other DFN2020-6 dual MOSFETs?

No - PMDPB30XNAX uses a non-standard pinout: pins 1/S1, 2/G1, 3/D2, 4/S2, 5/G2, 6/D1. Unlike common dual-N layouts (e.g., G1-S1-D1-G2-S2-D2), its interleaved drain-source arrangement requires specific PCB layout alignment and cannot be substituted without redesign.

What is the maximum continuous drain current per transistor at 100 °C ambient?

At T_amb = 100 °C with standard FR4 mounting (6 cm² drain pad), the maximum continuous drain current per transistor is 2.8 A - derived from Fig. 2 in the datasheet, where normalized current drops to 62% of the 25 °C value (4.5 A × 0.62 = 2.79 A).

Does PMDPB30XNAX support reverse-battery protection when used back-to-back?

Yes - when configured with one transistor's source tied to the other's drain and gates driven in parallel, the intrinsic body diodes block reverse current flow. The 0.7–1.2 V V_SD forward drop and 1.2 A source current rating support this topology at ≤2 A loads with <1.5 W dissipation.

How does the exposed drain pad affect solder reflow profile requirements?

The exposed pad requires full thermal mass consideration: IPC-7095-compliant reflow must achieve peak temperature ≥235 °C for ≥30 s to ensure void-free solder joint formation. Footprint per Fig. 19 specifies 0.875 mm × 0.875 mm solder land with 0.49 mm paste aperture for optimal thermal transfer and mechanical reliability.