Nexperia USA Inc. PMDPB70XPE,115

Overview

PMDPB70XPE,115 from Nexperia is a dual P-channel enhancement-mode Trench MOSFET in a DFN2020-6 (SOT1118) package, designed for high-side load switching and relay driving. It delivers -20 V drain-source voltage rating, 66 mΩ typical R_DS(on) at V_GS = -4.5 V and I_D = -2 A, 2 kV HBM ESD protection, and fast switching with 7 ns turn-on delay and 15 ns fall time. Used in compact DC-DC power stages and industrial I/O modules.

For engineers reviewing the PMDPB70XPE,115 datasheet, PMDPB70XPE,115 pinout, PMDPB70XPE,115 application, or PMDPB70XPE,115 equivalent, this device is selected for space-constrained dual high-side switch designs requiring low conduction loss, robust gate drive margin, and thermal efficiency on FR4 PCBs with 6 cm² drain pad.

Technical Context

This dual P-channel MOSFET integrates two independent Trench-based transistors sharing no internal connection-each with isolated source, gate, and drain terminals. Its symmetric layout supports independent control of TR1 and TR2, enabling true dual high-side switching without cross-talk or shared thermal coupling under transient loads.

The device operates with gate threshold voltage (V_GS(th)) between -0.75 V and -1.25 V at 25 °C, ensuring reliable turn-on with standard 3.3 V or 5 V logic-level gate drivers. Its 77 pF reverse transfer capacitance (Cr_ss) and 600 pF input capacitance (C_iss) support stable high-frequency switching up to 1 MHz while minimizing Miller-induced shoot-through risk.

Key Specifications

Pinout & Package

DFN2020-6 (SOT1118) is a 2.0 mm × 2.0 mm × 0.65 mm leadless thermally enhanced plastic package with exposed drain pads on both sides. The bottom-side thermal pad improves heat transfer to PCB copper, while top-side marking "2B" identifies the PMDPB70XPE variant.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual P-channel MOSFET applications.

Compared with DMN601WKQ-7 and PSMN2R0-30YLC, PMDPB70XPE,115 uniquely balances ultra-compact size (2.0 × 2.0 mm), low R_DS(on) (66 mΩ), and integrated dual topology-making it optimal for space-limited, medium-current (<4.2 A) high-side switching where thermal pad integration and ESD robustness are essential.

Availability

PMDPB70XPE,115 is available at Aetrix Electronics and suitable for industrial I/O modules, PLC output stages, and compact DC-DC power management systems requiring stable component supply, consistent parametric performance, and long-term manufacturing continuity.

Supply support for PMDPB70XPE,115 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on high-volume, high-reliability discrete and logic components, serving automotive, industrial, and consumer markets with ISO/TS 16949-certified manufacturing.

The PMDPB70XPE,115 belongs to Nexperia's TrenchMOS® dual FET product line, engineered specifically for space-efficient high-side switching in industrial control and power management applications demanding low R_DS(on), fast switching, and robust ESD tolerance.

FAQ

What is the maximum continuous drain current per channel at 100 °C ambient temperature?

The PMDPB70XPE,115 supports -2.1 A continuous drain current per transistor at Tamb = 100 °C, as specified in Table 5 Limiting Values. This rating assumes mounting on an FR4 PCB with single-sided copper, tin-plated, and a 6 cm² drain pad. Derating follows the normalized curve in Figure 2, where current drops linearly from -4.2 A at 25 °C to -2.1 A at 100 °C.

Can the two transistors share a common gate drive signal?

Yes, G1 and G2 can be paralleled for simultaneous switching, but only if both channels drive identical loads and thermal conditions are matched. Independent gate routing is recommended to prevent timing skew, especially in PWM or phase-controlled applications where mismatched turn-on delays could cause shoot-through or current imbalance.

Is the DFN2020-6 (SOT1118) package compatible with standard reflow profiles?

Yes-the DFN2020-6 package is qualified for IPC/JEDEC J-STD-020D-compliant lead-free reflow. Recommended peak temperature is 260 °C for ≤30 seconds, with ramp rates ≤3 °C/s pre-peak. Figure 19 provides the exact solder paste stencil and land pattern dimensions required to ensure void-free thermal pad wetting and mechanical reliability.

Does the device include internal body diode protection for inductive loads?

Each transistor includes an inherent source-drain body diode with V_SD = -0.7 to -1.2 V at I_S = -0.5 A and T_j = 25 °C (Table 7). This diode conducts reverse current during inductive flyback but is not rated for sustained avalanche energy; external freewheeling diodes or snubbers are required for repetitive inductive switching above 100 kHz.