Nexperia USA Inc. PMDPB80XP,115

Overview

PMDPB80XP,115 from Nexperia is a dual P-channel enhancement-mode Trench MOSFET in a DFN2020-6 (SOT1118) package, rated for −20 V drain-source voltage, 80 mΩ typical R_DS(on) at V_GS = −4.5 V, and −3.7 A continuous drain current per transistor. It serves as a compact, thermally efficient power switch in portable battery management and DC/DC converter topologies.

For engineers reviewing the PMDPB80XP,115 datasheet, PMDPB80XP,115 pinout, PMDPB80XP,115 application, or PMDPB80XP,115 equivalent, this device is selected for low-voltage gate drive compatibility (1.8 V threshold), ultra-thin SMD footprint (2 × 2 × 0.65 mm), and dual-channel integration enabling space-constrained high-efficiency load switching.

Technical Context

This dual P-channel MOSFET uses Trench technology to achieve low on-resistance and fast switching with minimal gate charge (Q_G(tot) = 5.7–8.6 nC). Each channel operates independently with matched characteristics: V_GS(th) = −0.4 to −1.0 V, and R_DS(on) increases predictably with junction temperature (116–148 mΩ at 150 °C).

The exposed drain pad provides direct thermal conduction to PCB copper, supporting 1100 mW total power dissipation under optimized mounting (6 cm² drain pad). Safe operating area (SOA) is defined up to 11 A peak drain current with 10 µs pulse width, enabling robust transient handling in motor drive and charging control circuits.

Key Specifications

Pinout & Package

Package: DFN2020-6 (SOT1118), 2.0 × 2.0 × 0.65 mm, leadless, thermally enhanced with exposed drain pad.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual P-channel MOSFET applications.

Compared with DMC2038LSD-7 and SI3993DV-T1-GE3, PMDPB80XP,115 delivers superior thermal density (0.65 mm height, exposed pad), matched dual-channel timing, and lowest R_DS(on) in its footprint class - making it optimal for space- and thermally constrained portable power systems.

Availability

PMDPB80XP,115 is available at Aetrix Electronics and suitable for portable device charging switches, DC/DC converter high-side switching, and small BLDC motor drive applications requiring stable component supply, long-term lifecycle support, and consistent parametric performance across production batches.

Supply support for PMDPB80XP,115 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on high-volume, high-reliability discrete and logic devices, with leadership in automotive-qualified and industrial-grade components.

The PMDPB80XP,115 belongs to Nexperia's TrenchMOS P-channel portfolio, engineered specifically for low-voltage, high-efficiency power switching in space-constrained portable electronics where thermal management and gate drive simplicity are critical.

FAQ

What is the maximum continuous drain current per channel at 100 °C ambient?

At T_amb = 100 °C, the maximum continuous drain current per channel is −1.7 A, as specified in Table 5 (Limiting Values) under "ID drain current" with condition V_GS = −4.5 V and T_amb = 100 °C. This derating reflects thermal limitations of the DFN2020-6 package without forced airflow or extended copper pour.

Can PMDPB80XP,115 be used in a synchronous buck converter as both high-side and low-side switch?

No - PMDPB80XP,115 is a dual P-channel device and lacks integrated body diodes optimized for synchronous rectification. Its source-drain diode V_SD is −0.8 to −1.2 V at −1.1 A, but it is not rated for reverse recovery in low-side switching. It is intended only for high-side or load-switch roles where unidirectional blocking is required.

Is the exposed drain pad electrically connected to both D1 and D2 terminals?

Yes - per the pinning diagram (Table 2) and package outline (Figure 18), the exposed drain pad is internally connected to both D1 (pin 6) and D2 (pin 3), forming a common thermal and electrical node for both transistors. This configuration enables shared heat dissipation but requires that both drains be at the same potential in the circuit.

What is the gate charge required to fully turn on one channel?

The total gate charge Q_G(tot) per channel is 5.7–8.6 nC at V_DS = −10 V, I_D = −2.7 A, and V_GS = −4.5 V (Table 7). This value represents the charge needed to drive the gate from 0 V to −4.5 V while transitioning through the Miller plateau, directly determining gate driver current and switching loss.