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Nexperia USA Inc. PMDXB950UPEZ

Part No.:
PMDXB950UPEZ
Manufacturer:
Nexperia USA Inc.
Category:
FET, MOSFET Arrays
Package:
6-XFDFN Exposed Pad
Datasheet:
AetrixPMDXB950UPEZ.pdf
Description:
MOSFET 2P-CH 20V 0.5A 6DFN
Quantity:
Payment:
Payment
Shipping:
Shipping

Inventory:11,750

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Product details

Overview

PMDXB950UPEZ from Nexperia is a dual P-channel enhancement-mode Trench MOSFET in a DFN1010B-6 (SOT1216) package, designed for high-side load switching and relay driving in space-constrained portable electronics. It delivers RDS(on) = 1.02 Ω at VGS = −4.5 V, supports −20 V drain-source voltage, −500 mA continuous drain current per channel, and features an exposed drain pad for thermal conduction.

For engineers reviewing the PMDXB950UPEZ datasheet, PMDXB950UPEZ pinout, PMDXB950UPEZ application, or PMDXB950UPEZ equivalent, this device is selected for ultra-compact dual high-side switching where low gate charge (QG(tot) = 1.19 nC), ESD protection >1 kV HBM, and thermal resistance Rth(j-sp) = 27 K/W are critical design factors.

Technical Context

This dual P-channel MOSFET integrates two independent enhancement-mode transistors sharing no internal connection-each with separate source, gate, and drain terminals. Its Trench MOSFET architecture enables low RDS(on) and fast switching (td(on) = 2.3 ns, tf = 6 ns) under −4.5 V gate drive, optimized for logic-level control from 3.3 V or 5 V microcontrollers.

The DFN1010B-6 package uses an exposed drain pad soldered directly to PCB copper for thermal management, supporting 4025 mW peak power dissipation when mounted on a 1 cm² drain pad. Gate threshold voltage (VGS(th)) ranges from −0.45 V to −0.95 V, ensuring reliable turn-on with modest negative gate bias.

Key Specifications

Parameter Value and Actual Design Meaning
VDS −20 V - Maximum blocking voltage per transistor; suitable for 12 V rail switching with margin.
RDS(on) 1.02 Ω (typ) at VGS = −4.5 V, ID = −500 mA - Enables <100 mW conduction loss per channel at rated current.
QG(tot) 1.19 nC (typ) - Low gate charge reduces driver power demand and speeds switching transitions.
VGS(th) −0.7 V (typ) - Ensures full enhancement with common logic-level gate drivers operating down to 3.3 V.
Rth(j-sp) 27 K/W (typ) - Junction-to-solder-point thermal resistance enables efficient heat transfer to PCB copper.
ID (cont) −500 mA per transistor at Tamb = 25 °C - Sustained current capability for compact load switches without forced cooling.
ESD HBM >1 kV - Built-in electrostatic discharge protection simplifies board-level ESD design.

Pinout & Package

Package: DFN1010B-6 (SOT1216), 1.1 × 1.0 × 0.37 mm, leadless, ultra-thin surface-mount package with exposed drain pad for thermal conduction.

Pin/Terminal Circuit Role Design Meaning
1 S1 Source of transistor TR1 - Connected to load return path; electrically isolated from S2.
2 G1 Gate of transistor TR1 - Controls TR1 conduction; requires negative voltage relative to S1.
3 D2 Drain of transistor TR2 - High-side switch output node for second channel.
4 S2 Source of transistor TR2 - Independent return path for second load; not internally tied to S1.
5 G2 Gate of transistor TR2 - Independently controllable gate input for second channel.
6 D1 Drain of transistor TR1 - Primary high-side switch output node; shares exposed pad with D2.

Key Features

Feature Design Value
Trench MOSFET architecture Enables 1.02 Ω RDS(on) at −4.5 V drive while maintaining fast 2.3 ns turn-on delay.
Exposed drain pad Reduces Rth(j-sp) to 27 K/W, allowing 4025 mW peak power handling with proper PCB layout.
Ultra-small footprint 1.1 × 1.0 mm DFN1010B-6 saves >60% board area versus comparable SO-8 dual MOSFETs.
ESD protection HBM rating >1 kV eliminates need for external ESD diodes in most portable designs.
Low gate charge 1.19 nC total gate charge minimizes gate driver losses and supports >1 MHz switching.

Applications

Relay Driver High-Speed Line Driver

Use Scenario: Replacing mechanical relays in battery-powered IoT sensor nodes requiring silent, wear-free switching.

IC Role / Device Role / Timing Role: Dual high-side switch controlling coil current for two independent relays with independent enable control.

Use Value: Eliminates relay bounce and contact wear; 1.02 Ω RDS(on) limits coil heating to <100 mW per channel at 500 mA.

Use Scenario: Driving differential signaling lines in USB 2.0 or MIPI D-PHY interfaces within handheld medical devices.

IC Role / Device Role / Timing Role: Active termination switch enabling dynamic impedance matching and signal integrity control.

Use Value: 6 ns fall time and 2.3 ns turn-on delay support clean edge transitions up to 100 Mbps data rates.

High-Side Load Switch Switching Power Supply Auxiliary Control

Use Scenario: Power sequencing for multiple subsystems (e.g., display backlight, sensor array, radio module) in wearable fitness trackers.

IC Role / Device Role / Timing Role: Dual independent high-side power switches enabling staggered power-up and fault-isolated shutdown.

Use Value: −500 mA per channel supports typical subsystem loads; exposed drain pad maintains junction temperature <105 °C at full load.

Use Scenario: Enabling/disabling auxiliary rails (e.g., bias supplies, reference voltages) in buck-boost DC-DC converters for industrial sensors.

IC Role / Device Role / Timing Role: Precision-controlled high-side switch for sequencing auxiliary power domains synchronized with main converter startup.

Use Value: −0.7 V VGS(th) ensures reliable turn-on with 3.3 V logic; 14 pF Coss prevents coupling noise into sensitive analog sections.

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual P-channel high-side switching applications.

Alternative Part Technical Difference Application Difference Selection Advice
DMC2038LVT RDS(on) = 1.2 Ω at −4.5 V; larger DFN1212-6 package (1.2 × 1.2 mm); QG(tot) = 1.4 nC Higher thermal resistance (Rth(j-sp) = 35 K/W); less suitable for ultra-dense layouts Prefer when higher surge current (IDM = −3 A) is required over minimal footprint.
SI3993DV RDS(on) = 0.95 Ω at −4.5 V; same DFN1010B-6 footprint; QG(tot) = 1.35 nC; no specified ESD rating Lacks documented HBM ESD protection; requires external clamping in harsh environments Choose when lowest RDS(on) is prioritized and board-level ESD design is fully controlled.

Compared with PMDXB950UPEZ, DMC2038LVT trades 0.18 Ω higher RDS(on) for greater surge robustness, while SI3993DV offers marginally lower conduction loss but omits integrated ESD protection-making PMDXB950UPEZ optimal for space- and reliability-critical portable designs.

Availability

PMDXB950UPEZ is available at Aetrix Electronics and suitable for portable medical monitors, battery-powered IoT endpoints, and compact industrial controllers requiring stable component supply with guaranteed long-term sourcing.

Supply support for PMDXB950UPEZ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert specializing in high-volume, high-reliability discrete and logic components, with core competencies in MOSFETs, ESD protection, and logic ICs.

The PMDXB950UPEZ belongs to Nexperia's TrenchMOS dual P-channel portfolio, engineered specifically for ultra-compact, thermally efficient high-side switching in battery-operated and space-constrained applications.

FAQ

What is the maximum continuous drain current per channel at 100 °C ambient?

At Tamb = 100 °C, the maximum continuous drain current per channel is −300 mA, as specified in Table 5 (Limiting values). This derating accounts for thermal resistance and junction temperature limits; operation above this requires active cooling or reduced duty cycle.

Can PMDXB950UPEZ be used with 3.3 V GPIO for gate control?

Yes-its VGS(th) range (−0.45 V to −0.95 V) ensures full enhancement with 3.3 V logic when referenced to source. A −3.3 V gate drive (i.e., GPIO pulled low while source is at system VDD) achieves VGS = −3.3 V, well within the −4.5 V test condition for RDS(on).

Is the exposed drain pad electrically connected to any pin?

Yes-the exposed drain pad is internally connected to both D1 (pin 6) and D2 (pin 3), forming a common thermal and electrical node. It must be soldered to a dedicated PCB copper pour to achieve specified Rth(j-sp) and power dissipation ratings.

Does PMDXB950UPEZ include body diode conduction capability?

Yes-each transistor includes an intrinsic source-drain diode with VSD = −0.7 V to −1.2 V at IS = −115 mA. This enables reverse-current freewheeling in inductive load applications, though forward conduction is limited by the P-channel structure and should be verified against safe operating area curves.

PMDXB950UPEZ Specifications

Product attributes
Attribute value
Manufacturer:
Nexperia USA Inc.
Series:
-
Package/Case:
6-XFDFN Exposed Pad
Packaging:
Tape & Reel (TR)
Product Status:
Active
Technology:
MOSFET (Metal Oxide)
Configuration:
2 P-Channel (Dual)
FET Feature:
Logic Level Gate
Drain to Source Voltage (Vdss):
20V
Current - Continuous Drain (Id) @ 25°C:
500mA
Rds On (Max) @ Id, Vgs:
1.4Ohm @ 500mA, 4.5V
Vgs(th) (Max) @ Id:
950mV @ 250µA
Gate Charge (Qg) (Max) @ Vgs:
2.1nC @ 4.5V
Input Capacitance (Ciss) (Max) @ Vds:
43pF @ 10V
Power - Max:
265mW
Operating Temperature:
-55°C ~ 150°C (TJ)
Grade:
-
Qualification:
-
Mounting Type:
Surface Mount
Supplier Device Package:
DFN1010B-6

PMDXB950UPEZ FAQ

1.How can I place an order for PMDXB950UPEZ through Aetrix?

Please submit a Request for Quotation (RFQ) for PMDXB950UPEZ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for PMDXB950UPEZ reliable?

The price and inventory of PMDXB950UPEZ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PMDXB950UPEZ is usually 5 days.

3.What payment methods are accepted for PMDXB950UPEZ?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PMDXB950UPEZ transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for PMDXB950UPEZ?

PMDXB950UPEZ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your PMDXB950UPEZ order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for PMDXB950UPEZ?

For technical support, including PMDXB950UPEZ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PMDXB950UPEZ requirements.

6.How does Aetrix verify that PMDXB950UPEZ is sourced from the original manufacturer or authorized distributors?

All PMDXB950UPEZ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PMDXB950UPEZ meets industry standards.

7.What is the process for return or replacement of PMDXB950UPEZ?

All PMDXB950UPEZ units undergo pre-shipment inspection (PSI). If there is an issue with PMDXB950UPEZ, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The PMDXB950UPEZ part is unused and in its original packaging.

Return procedure for PMDXB950UPEZ:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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