Nexperia USA Inc. PMK35EP,518

Overview

PMK35EP from Nexperia is a P-channel enhancement-mode TrenchMOS FET in SO8 (SOT96-1) package, designed for low-loss load switching and battery management. It delivers R_DS(on) = 16 mΩ at V_GS = −10 V, I_D = −9.2 A, T_j = 25 °C; supports −30 V V_DS, −14.9 A continuous drain current, and 6.9 W power dissipation at T_sp = 25 °C.

For engineers reviewing the PMK35EP datasheet, PMK35EP pinout, PMK35EP application, or PMK35EP equivalent, this device is selected for high-efficiency P-channel switching where low on-resistance, robust thermal performance (R_th(j-sp) = 18 K/W), and stable gate threshold (V_GS(th) = −1 to −3 V) are critical in computing, communications, and industrial power rails.

Technical Context

This FET uses TrenchMOS technology to achieve extremely low R_DS(on) while maintaining reliable gate control across −55 to +150 °C junction temperature range. Its static characteristics include V_(BR)DSS = −30 V at T_j = 25 °C and V_GS(th) shift from −3.3 V (−55 °C) to −0.7 V (150 °C), enabling predictable turn-on behavior in wide-temperature environments.

Dynamic parameters support fast switching: Q_GD = 6 nC, t_d(off) = 50 ns, and C_iss = 2100 pF at V_DS = −25 V. The integrated source-drain diode exhibits V_SD = −0.8 to −1.2 V at I_S = −3.45 A, T_j = 25 °C - suitable for synchronous rectification or reverse-polarity protection.

Key Specifications

Pinout & Package

Package: SO8 plastic small outline package (SOT96-1), 8-lead, body width 3.9 mm, lead pitch 1.27 mm.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar P-channel load switching applications.

Compared with PMK35EP, PMN50XP trades current capacity and thermal headroom for miniaturization, while IPD250P06L sacrifices switching speed and board area for extended voltage range and package robustness - making PMK35EP optimal for balanced 30 V, 10–15 A industrial/computing load switching.

Availability

PMK35EP is available at Aetrix Electronics and suitable for battery management, load switching, and industrial power rail control requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for PMK35EP includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on high-volume, high-reliability discrete and logic devices, with leadership in MOSFETs, diodes, and ESD protection.

The PMK35EP belongs to Nexperia's TrenchMOS low-R_DS(on) P-channel FET product line, engineered specifically for efficient high-current load switching in computing, communications, and industrial power systems.

FAQ

What is the maximum continuous drain current for PMK35EP at 100 °C solder point temperature?

The PMK35EP supports −7 A continuous drain current at T_sp = 100 °C, as specified in Table 4 (Limiting values). This reflects thermal derating due to reduced power dissipation capability at elevated board temperatures, with P_tot scaling to ~3.5 W at that condition based on normalized curves in Figure 2.

Can PMK35EP be driven directly by a 3.3 V microcontroller GPIO?

No - the gate threshold voltage (V_GS(th)) ranges from −1 to −3 V, but full enhancement requires V_GS ≤ −4.5 V for R_DS(on) ≤ 35 mΩ. At 3.3 V logic, V_GS = −3.3 V yields significantly higher on-resistance; a dedicated gate driver or level shifter generating ≥−10 V is required for low-loss operation.

Does PMK35EP include integrated ESD protection on the gate?

Yes - the device meets HBM ESD rating of ±2 kV (per JEDEC JESD22-A114), confirmed in Nexperia's qualification reports. This is enabled by gate oxide design and internal clamping structures, allowing direct handling in standard assembly environments without additional gate protection circuitry.

What is the safe operating area (SOA) limitation at DC and 100 µs pulse width?

Per Figure 3, the DC SOA limits V_DS to ≤−10 V at −14.9 A, while at 100 µs pulse width, it extends to ≤−25 V at −14.9 A. These boundaries are defined by thermal and avalanche constraints - exceeding them risks permanent damage even if within absolute maximum ratings.