Nexperia USA Inc. PMPB12R5EPX
- Part No.:
- PMPB12R5EPX
- Manufacturer:
- Nexperia USA Inc.
- Category:
- FETs, MOSFETs
- Package:
- 6-UDFN Exposed Pad
- Datasheet:
-
PMPB12R5EPX.pdf
- Description:
- PMPB12R5EP - 30 V, P-CHANNEL TRE
- Quantity:
- Payment:

- Shipping:

Inventory:4,992
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Product details
Overview
PMPB12R5EPX from Nexperia is a P-channel enhancement-mode Trench MOSFET in a DFN2020M-6 (SOT1220-2) package, rated for −30 V drain-source voltage, 12.5 mΩ RDS(on) at VGS = −10 V and ID = −8.8 A, and −12.5 A continuous drain current at Tamb = 25 °C. It serves as a high-efficiency charging switch or power rail control device in compact portable electronics.
For engineers reviewing the PMPB12R5EPX datasheet, PMPB12R5EPX pinout, PMPB12R5EPX application, or PMPB12R5EPX equivalent, key selection criteria include logic-level gate drive compatibility (VGS(th) = −1.6 V typ), ultra-thin 2 × 2 × 0.65 mm thermal-enhanced package, exposed drain pad for low Rth(j-sp), and verified performance in battery-powered DC-DC converter output stages.
Technical Context
This MOSFET employs Trench technology to achieve low on-resistance and fast switching with QG(tot) = 29–44 nC and td(off) = 121 ns. Its gate threshold voltage (−1.6 V typ) ensures reliable turn-on with 3.3 V or 5 V logic controllers without level-shifting.
The device features an integrated source-drain diode with VSD = −0.7 to −1.2 V at IS = −1.9 A and exhibits stable RDS(on) over temperature (20–24 mΩ at Tj = 150 °C), supporting robust operation in thermally constrained portable designs.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VDS | −30 V - Maximum blocking voltage for battery-side high-side switching in 3.3 V/5 V systems |
| RDS(on) | 12.5 mΩ (typ) at VGS = −10 V, ID = −8.8 A, Tj = 25 °C - Enables <100 mW conduction loss at 8 A load |
| ID (cont) | −12.5 A at Tamb = 25 °C, t ≤ 5 s - Supports short-duration peak loads in USB-C PD or power bank discharge paths |
| VGS(th) | −1.6 V (typ) at ID = −250 µA - Ensures full enhancement with standard 3.3 V GPIOs without external bias |
| QG(tot) | 29–44 nC - Low gate charge enables efficient PWM control up to 1 MHz in synchronous buck converters |
| Rth(j-sp) | 6–10 K/W - Exposed drain pad delivers rapid heat transfer to PCB copper, critical for 2 × 2 mm footprint thermal management |
| Ciss | 1392 pF - Input capacitance supports stable gate drive with standard 6 Ω series resistance and minimal ringing |
Pinout & Package
DFN2020M-6 (SOT1220-2) is a leadless, ultra-thin surface-mount package measuring 2.0 × 2.0 × 0.65 mm with an exposed drain pad on the bottom for enhanced thermal conduction. The top-side terminals are arranged in a single row of six positions with pin 1 index marking.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | Drain | Primary high-current path; electrically and thermally connected to exposed bottom pad |
| 2 | Drain | Parallel drain connection to reduce current density and improve thermal spreading |
| 3 | Gate | Control terminal; requires ESD-safe handling and low-inductance layout due to 21 Ω internal gate resistance |
| 4 | Source | Reference node for gate drive; tied to system ground or battery negative in high-side switch configurations |
| 5 | Drain | Third parallel drain terminal; contributes to <6 K/W junction-to-solder-point thermal resistance |
| 6 | Source | Second source connection; improves current sharing and reduces source inductance in high-dI/dt applications |
Key Features
| Feature | Design Value |
|---|---|
| Logic-level gate drive | VGS(th) = −1.6 V typ enables direct interface with 3.3 V microcontrollers without level shifters |
| Thermal-enhanced DFN package | Exposed drain pad and 2 × 2 mm footprint deliver Rth(j-sp) as low as 6 K/W for sustained 8 A operation |
| Trench MOSFET architecture | Optimized cell structure achieves 12.5 mΩ RDS(on) while maintaining 35 A peak pulsed current capability |
| Ultra-thin profile | 0.65 mm max height allows integration into space-constrained mobile PCBs with stacked components |
| Low gate charge | QG(tot) = 29–44 nC minimizes driver power loss and enables high-frequency (>500 kHz) switching in DC-DC regulators |
Applications
| USB-C Power Delivery Switch | Portable Device Battery Protection |
|---|---|
Use Scenario: High-side switching of 5–20 V input rails in USB-C PD sink devices during voltage negotiation and fault isolation. IC Role / Device Role / Timing Role: P-channel MOSFET configured as load switch with controlled turn-on slew rate to prevent inrush current. Use Value: 12.5 mΩ RDS(on) limits voltage drop to <100 mV at 8 A, preserving PD compliance margins while enabling compact 2 × 2 mm board area. |
Use Scenario: Reverse-polarity and overcurrent protection in lithium-ion battery packs for tablets and wearables. IC Role / Device Role / Timing Role: Bidirectional blocking element placed between battery terminals and system load, activated only during fault conditions. Use Value: −30 V VDS rating accommodates battery stack voltages up to 3S (12.6 V) with 2.4× safety margin; low VGS(th) ensures fast response to protection IC signals. |
| DC-DC Converter Synchronous Rectifier | Computing Power Rail Control |
Use Scenario: Low-side synchronous rectification in 3.3 V or 5 V buck converters powering SoCs in handheld devices. IC Role / Device Role / Timing Role: Fast-switching power transistor replacing Schottky diode to reduce conduction loss and improve efficiency. Use Value: QGD = 5.4 nC and tf = 53 ns support clean zero-voltage switching transitions at 1 MHz, cutting rectifier losses by >40% vs. discrete diodes. |
Use Scenario: Controlled power-up sequencing and dynamic rail enable/disable in notebook motherboard VRMs and peripheral controllers. IC Role / Device Role / Timing Role: High-reliability power switch managing 3.3 V or 5 V auxiliary rails with precise timing via GPIO control. Use Value: −12.5 A continuous rating and 35 A peak current handle transient surges during CPU core activation; 21 Ω gate resistance damps oscillation without external resistor. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar P-channel load switch applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| DMG2305UVT-7 | RDS(on) = 42 mΩ @ VGS = −4.5 V; SOT-23 package; higher Rth(j-a) (223 K/W) | Lower current capacity (−4.2 A); suitable only for sub-2 A loads with relaxed thermal constraints | Select when board space permits larger SOT-23 and thermal budget exceeds 1 W at 3 A |
| SI2305DS-T1-E3 | RDS(on) = 55 mΩ @ VGS = −4.5 V; same SOT-23 footprint; no exposed thermal pad | Limited to ≤1.5 A continuous; lacks thermal performance for sustained high-current switching | Choose only for cost-sensitive, low-power applications where 2 × 2 mm footprint is not required |
Compared with DMG2305UVT-7 and SI2305DS-T1-E3, PMPB12R5EPX delivers 3.4× lower RDS(on), 30× better thermal resistance, and 2.5× higher continuous current in half the footprint-making it the sole viable option for ≥5 A portable power switches requiring <100 mW conduction loss.
Availability
PMPB12R5EPX is available at Aetrix Electronics and suitable for USB-C power delivery modules, portable battery protection circuits, and computing power rail control requiring stable component supply across high-volume consumer electronics production.
Supply support for PMPB12R5EPX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on high-performance, energy-efficient logic, discrete, and MOSFET solutions for automotive, industrial, and consumer markets.
The PMPB12R5EPX belongs to Nexperia's TrenchMOS portfolio, engineered specifically for high-density portable power management where low RDS(on), logic-level drive, and ultra-thin packaging are mandatory.
FAQ
What is the maximum continuous drain current for PMPB12R5EPX at 100 °C ambient temperature?
The maximum continuous drain current is −5.6 A at Tamb = 100 °C, as specified in Table 5 (Limiting values). This derating reflects thermal limits under standard FR4 PCB mounting with 6 cm² drain pad; actual current depends on board layout and airflow.
Does PMPB12R5EPX require a gate resistor for stable switching in a 1 MHz DC-DC converter?
No external gate resistor is required for stability-the device has an internal gate resistance of 21 Ω (Table 7), which sufficiently damps ringing when driven directly by typical 3.3 V PWM controllers. Layout best practices (short gate trace, ground plane proximity) remain essential.
Can PMPB12R5EPX be used in a high-side switch configuration with 3.3 V logic control?
Yes. With VGS(th) = −1.6 V (typ), the device fully enhances at VGS = −3.3 V, making it compatible with 3.3 V microcontroller GPIOs driving the gate referenced to the source (i.e., source tied to load side, drain to supply).
What is the thermal resistance from junction to solder point (Rth(j-sp)) and how is it measured?
Rth(j-sp) is 6–10 K/W (Table 6), measured with the device mounted on an FR4 PCB with single-sided copper, tin-plated, and a 6 cm² drain mounting pad. This value quantifies heat flow from die to PCB copper, critical for predicting junction temperature rise under load.
PMPB12R5EPX Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- TrenchMOS™
- Package/Case:
- 6-UDFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- FET Type:
- P-Channel
- Technology:
- MOSFET (Metal Oxide)
- Drain to Source Voltage (Vdss):
- 30 V
- Current - Continuous Drain (Id) @ 25°C:
- 8.8A (Ta)
- Drive Voltage (Max Rds On, Min Rds On):
- 4.5V, 10V
- Rds On (Max) @ Id, Vgs:
- 15mOhm @ 8.8A, 10V
- Vgs(th) (Max) @ Id:
- 2V @ 250µA
- Gate Charge (Qg) (Max) @ Vgs:
- 44 nC @ 10 V
- Vgs (Max):
- ±20V
- Input Capacitance (Ciss) (Max) @ Vds:
- 1392 pF @ 15 V
- FET Feature:
- -
- Power Dissipation (Max):
- 1.9W (Ta), 12.5W (Tc)
- Operating Temperature:
- -55°C ~ 150°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- DFN2020M-6
PMPB12R5EPX FAQ
1.How can I place an order for PMPB12R5EPX through Aetrix?
Please submit a Request for Quotation (RFQ) for PMPB12R5EPX on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PMPB12R5EPX reliable?
The price and inventory of PMPB12R5EPX are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PMPB12R5EPX is usually 5 days.
3.What payment methods are accepted for PMPB12R5EPX?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PMPB12R5EPX transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PMPB12R5EPX?
PMPB12R5EPX orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PMPB12R5EPX order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PMPB12R5EPX?
For technical support, including PMPB12R5EPX datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PMPB12R5EPX requirements.
6.How does Aetrix verify that PMPB12R5EPX is sourced from the original manufacturer or authorized distributors?
All PMPB12R5EPX products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PMPB12R5EPX meets industry standards.
7.What is the process for return or replacement of PMPB12R5EPX?
All PMPB12R5EPX units undergo pre-shipment inspection (PSI). If there is an issue with PMPB12R5EPX, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PMPB12R5EPX part is unused and in its original packaging.
Return procedure for PMPB12R5EPX:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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