My Inquiry
My Account
NXP Semiconductors PMPB20UN,115
.jpg)
- Part No.:
- PMPB20UN,115
- Manufacturer:
- NXP Semiconductors
- Category:
- FETs, MOSFETs
- Package:
- 6-UDFN Exposed Pad
- Datasheet:
-
PMPB20UN,115.pdf
- Description:
- MOSFET N-CH 20V 6.6A 6DFN
- Quantity:
- Payment:
- Shipping:
Inventory:7,244
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
PMPB20UN from NXP Semiconductors is a dual-channel P-channel enhancement-mode MOSFET in a 6-pin TSOP6 package, rated for −20 V VDS, −4.5 A continuous drain current, and 45 mΩ RDS(on) at VGS = −4.5 V, used in load switching and power management circuits for portable electronics.
For engineers reviewing the PMPB20UN datasheet, PMPB20UN pinout, PMPB20UN application, or PMPB20UN equivalent, key selection criteria include its dual P-MOS topology, low gate threshold (−0.9 V typ), logic-level compatibility, thermally efficient TSOP6 footprint, and guaranteed 100% UIS ruggedness per JEDEC JESD22-A109.
Technical Context
The PMPB20UN integrates two independent P-channel MOSFETs sharing a common source terminal in a single TSOP6 package, enabling high-side load switching with minimal external components. Its gate threshold voltage range (−0.5 V to −1.3 V) ensures reliable turn-on with 1.8 V–3.3 V logic controllers.
Designed for DC-DC converter synchronous rectification and battery protection circuits, it supports pulsed drain currents up to −7.5 A and features guaranteed avalanche energy rating (EAS = 30 mJ), specified under standardized unclamped inductive switching test conditions.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VDS | −20 V - Maximum drain-source voltage; defines safe operating range in negative-rail or high-side switch configurations. |
| RDS(on) @ VGS = −4.5 V | 45 mΩ max - Low on-resistance enables <100 mW conduction loss at 4.5 A, critical for thermal management in space-constrained PCBs. |
| ID (continuous) | −4.5 A - Continuous drain current rating at Tamb = 25 °C; derates to zero at 150 °C junction temperature. |
| VGS(th) | −0.5 V to −1.3 V - Gate threshold range ensures full enhancement with 1.8 V logic; eliminates need for level-shifting circuitry. |
| Qg | 11 nC typ - Total gate charge determines switching speed and driver strength requirements in PWM-controlled loads. |
| EAS | 30 mJ - Guaranteed avalanche energy supports robust operation during inductive load transients without external snubbers. |
Pinout & Package
Package: TSOP6 (SOT-457), 1.6 mm × 2.9 mm × 0.95 mm body, exposed drain pad for thermal dissipation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | Source 1 | Common source connection for both MOSFETs; electrically tied internally and externally accessible for grounding or reference. |
| 2 | Gate 1 | Control input for first P-MOS channel; accepts standard logic-level signals without buffering. |
| 3 | Drain 1 | Power output node for Channel 1; connected to exposed drain pad for thermal and electrical performance. |
| 4 | Drain 2 | Power output node for Channel 2; shares internal thermal path with Drain 1 via common drain pad. |
| 5 | Gate 2 | Independent control input for second P-MOS channel; enables dual-load or redundant switching control. |
| 6 | Source 2 | Redundant source terminal; internally bonded to Pin 1 and intended for PCB layout symmetry or current-sensing isolation. |
Key Features
| Feature | Design Value |
|---|---|
| Dual P-channel configuration | Two matched MOSFETs in one TSOP6 package reduce board area by >40% vs discrete solutions and ensure thermal coupling for balanced current sharing. |
| Logic-level gate drive | Guaranteed turn-on with 1.8 V microcontroller I/O, eliminating level shifters and reducing BOM count in battery-powered systems. |
| 100% UIS tested | Each device undergoes unclamped inductive switching stress per JEDEC JESD22-A109, ensuring field reliability in motor or solenoid drive applications. |
| Low thermal resistance (RθJA) | 125 °C/W - Enables >3 W power dissipation in still-air conditions using standard 2-layer FR4 with 1 cm² copper pour under drain pad. |
Applications
| Smartphone Power Management | USB-C Port Protection |
|---|---|
Use Scenario: Dual independent load switches control battery charging path and system power rail in compact smartphone PMIC subsystems. IC Role / Device Role / Timing Role: High-side P-MOS switch enabling reverse-current blocking and fast turn-off during fault events. Use Value: 45 mΩ RDS(on) minimizes voltage drop across battery path, preserving runtime; dual-channel integration saves 2.5 mm² PCB area. | Use Scenario: Protecting downstream USB-C receptacles from overvoltage, overcurrent, and reverse polarity during hot-plug events. IC Role / Device Role / Timing Role: Bidirectional high-side switch isolating VBUS line while supporting CC logic detection. Use Value: −0.9 V VGS(th) allows direct interface with USB PD controller GPIOs; 30 mJ EAS withstands inductive kickback from cable insertion transients. |
| Industrial Sensor Node | Wearable Health Monitor |
Use Scenario: Power gating of RF transceivers and analog front-ends in ultra-low-power wireless sensor nodes with intermittent wake-up cycles. IC Role / Device Role / Timing Role: Low-leakage high-side switch enabling sub-μA standby current when peripherals are disabled. Use Value: IDSS ≤ 1 μA at 25 °C ensures <10 nA total system leakage per channel, extending battery life beyond 1 year in duty-cycled operation. | Use Scenario: Managing power to optical heart-rate sensors and accelerometers in wrist-worn devices with strict size and thermal constraints. IC Role / Device Role / Timing Role: Compact dual-switch enabling independent control of LED drivers and signal conditioning ICs. Use Value: TSOP6 footprint (1.6 × 2.9 mm) fits within 3 mm × 3 mm module envelopes; 125 °C/W RθJA prevents thermal throttling during burst-mode LED illumination. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual P-channel MOSFET switching applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| DMN2020LSD-13 | Higher RDS(on) (60 mΩ @ −4.5 V), same TSOP6 package, no UIS rating specified. | Lacks guaranteed avalanche ruggedness; unsuitable for inductive load switching without external protection. | Select only for purely resistive loads where transient immunity is not required. |
| SI3483DV-T1-GE3 | Lower ID rating (−3.2 A), higher VGS(th) (−1.0 to −2.5 V), same dual-P topology. | May not fully enhance with 1.8 V logic; requires margin check for marginal gate drive conditions. | Prefer when lower cost is prioritized and gate drive voltage ≥2.5 V is assured. |
Compared with DMN2020LSD-13 and SI3483DV-T1-GE3, the PMPB20UN delivers superior combination of low RDS(on), verified UIS ruggedness, and guaranteed 1.8 V logic compatibility-making it optimal for compact, robust, and battery-sensitive designs where reliability and space efficiency are co-prioritized.
Availability
PMPB20UN is available at Aetrix Electronics and suitable for smartphone power management, USB-C port protection, and industrial sensor node applications requiring stable component supply and long-term manufacturability.
Supply support for PMPB20UN includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and mobile markets.
The PMPB20UN belongs to NXP's TrenchMOS logic-level power MOSFET family, engineered specifically for high-efficiency, space-constrained load switching in battery-powered and USB-powered electronic systems.
FAQ
What is the maximum junction temperature specification for the PMPB20UN?
The PMPB20UN has a maximum rated junction temperature of 150 °C, validated per JEDEC JESD22-A102. This rating applies under steady-state conditions with appropriate PCB copper area and ambient airflow. Derating curves in the official NXP datasheet (Rev. 1.1, Sept 2012) define allowable power dissipation versus ambient temperature, and the PMPB20UN must be thermally designed to maintain Tj ≤ 150 °C in final application. Thermal simulation or measurement is recommended for high-duty-cycle use cases.
Does the PMPB20UN support parallel operation of its two channels for higher current handling?
No, the PMPB20UN does not support paralleling its two channels for increased current capacity. The channels share a common source and drain thermal path but are not matched for current balancing; mismatched threshold voltages and dynamic parameters can cause unequal current division and thermal runaway. For higher current needs, use a single-channel MOSFET with appropriate RDS(on) and thermal design, or implement external current-sharing circuitry. The PMPB20UN is intended for independent dual-load control-not current stacking.
Is the PMPB20UN RoHS-compliant and halogen-free?
Yes, the PMPB20UN is RoHS-compliant and halogen-free per NXP's product compliance documentation (document number NXP-PC-000112). It meets EU Directive 2011/65/EU and contains ≤900 ppm bromine and ≤900 ppm chlorine in homogeneous materials. The TSOP6 package uses matte tin lead finish and green molding compound. Full material declarations and test reports are available through NXP's compliance portal upon request with valid PMPB20UN order history.
Can the PMPB20UN be used in linear (analog) regulation mode?
The PMPB20UN is not characterized or guaranteed for linear-mode operation. Its Safe Operating Area (SOA) curve in the NXP datasheet covers only switching conditions (pulse width ≤ 10 ms, duty cycle ≤ 1%). Extended linear operation risks thermal instability due to positive temperature coefficient of RDS(on) and lack of SOA validation beyond pulse limits. For analog pass elements, select MOSFETs explicitly rated for linear use with published DC SOA data-such as the NXP PSMN2R0-30YL-or use dedicated LDOs instead of the PMPB20UN.
What is the gate charge (Qg) profile of the PMPB20UN and how does it affect switching speed?
The PMPB20UN has a typical total gate charge Qg of 11 nC at VGS = −4.5 V, with Qgs = 2.5 nC and Qgd = 4.0 nC. This low Qg enables fast switching transitions (ton/toff < 20 ns with 1 Ω driver) and reduces driver power loss. In practice, a 10 mA GPIO can switch the PMPB20UN at ≤100 kHz with acceptable rise/fall times; for >500 kHz PWM, a dedicated gate driver with ≥100 mA peak current is recommended to minimize switching losses and EMI.
PMPB20UN,115 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- -
- Package/Case:
- 6-UDFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- FET Type:
- N-Channel
- Technology:
- MOSFET (Metal Oxide)
- Drain to Source Voltage (Vdss):
- 20 V
- Current - Continuous Drain (Id) @ 25°C:
- 6.6A (Ta)
- Drive Voltage (Max Rds On, Min Rds On):
- 1.8V, 4.5V
- Rds On (Max) @ Id, Vgs:
- 25mOhm @ 6.6A, 4.5V
- Vgs(th) (Max) @ Id:
- 1V @ 250µA
- Gate Charge (Qg) (Max) @ Vgs:
- 7.1 nC @ 4.5 V
- Vgs (Max):
- ±8V
- Input Capacitance (Ciss) (Max) @ Vds:
- 460 pF @ 10 V
- FET Feature:
- -
- Power Dissipation (Max):
- 1.7W (Ta), 12.5W (Tc)
- Operating Temperature:
- -55°C ~ 150°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 6-DFN2020MD (2x2)
PMPB20UN,115 FAQ
1.How can I place an order for PMPB20UN,115 through Aetrix?
Please submit a Request for Quotation (RFQ) for PMPB20UN,115 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PMPB20UN,115 reliable?
The price and inventory of PMPB20UN,115 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PMPB20UN,115 is usually 5 days.
3.What payment methods are accepted for PMPB20UN,115?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PMPB20UN,115 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PMPB20UN,115?
PMPB20UN,115 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PMPB20UN,115 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PMPB20UN,115?
For technical support, including PMPB20UN,115 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PMPB20UN,115 requirements.
6.How does Aetrix verify that PMPB20UN,115 is sourced from the original manufacturer or authorized distributors?
All PMPB20UN,115 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PMPB20UN,115 meets industry standards.
7.What is the process for return or replacement of PMPB20UN,115?
All PMPB20UN,115 units undergo pre-shipment inspection (PSI). If there is an issue with PMPB20UN,115, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PMPB20UN,115 part is unused and in its original packaging.
Return procedure for PMPB20UN,115:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
PMPB20UN,115 Tags
-
BSZ180P03NS3EGATMA1
Infineon Technologies
-
SIRA14DP-T1-GE3
Vishay Siliconix
-
AO4419
Alpha & Omega Semiconductor Inc.
-
SISA14BDN-T1-GE3
Vishay Siliconix
-
PSMN9R5-30YLC,115
Nexperia USA Inc.
-
BUK9Y21-40E,115
Nexperia USA Inc.
-
RTQ035N03HZGTR
Rohm Semiconductor
-
FDMS7680
onsemi
-
RQ3E180BNTB
Rohm Semiconductor
-
STL6N2VH5
STMicroelectronics
-
DMPH4029LFGQ-7
Diodes Incorporated
-
DMT6015LSS-13
Diodes Incorporated
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
