Nexperia USA Inc. PMV65XPVL
- Part No.:
- PMV65XPVL
- Manufacturer:
- Nexperia USA Inc.
- Category:
- FETs, MOSFETs
- Package:
- TO-236-3, SC-59, SOT-23-3
- Datasheet:
-
PMV65XPVL.pdf
- Description:
- MOSFET P-CH 20V 2.8A TO236AB
- Quantity:
- Payment:

- Shipping:

Inventory:3,332
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
PMV65XPVL from Nexperia is a single P-channel enhancement-mode Trench MOSFET in SOT23 (TO-236AB) package, rated for −20 V drain-source voltage, 74 mΩ RDS(on) at VGS = −4.5 V and ID = −2.8 A, with −0.65 V typical gate threshold voltage. It serves as a low-side load switch or reverse-polarity protection device in space-constrained battery-powered systems.
For engineers reviewing the PMV65XPVL datasheet, PMV65XPVL pinout, PMV65XPVL application, or PMV65XPVL equivalent, this discrete MOSFET is selected for compact DC-DC converter high-side switching, portable equipment battery management, and low-voltage logic-level-controlled power path isolation where low gate charge (7.7 nC) and sub-1 V threshold enable direct microcontroller drive.
Technical Context
This P-channel MOSFET uses Trench MOSFET technology to achieve low on-resistance and fast switching with minimal gate drive requirements. Its −0.47 V to −0.9 V VGS(th) range ensures reliable turn-on with 1.8 V–3.3 V logic outputs, while its 1.65 nC QGD and 18 ns rise time support efficient operation in 1–5 MHz DC-DC converters.
The device features an integrated source-drain diode with −0.8 V to −1.2 V forward voltage at −0.9 A, enabling use in synchronous rectification or reverse-current blocking. Thermal resistance Rth(j-sp) of 25–30 K/W (drain pad mounted) supports sustained 2.8 A conduction under PCB thermal constraints typical of handheld devices.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VDS | −20 V - Maximum drain-source blocking voltage; suitable for 12 V rail and Li-ion battery (≤4S) systems. |
| RDS(on) | 58–74 mΩ @ VGS = −4.5 V, ID = −2.8 A - Enables ≤200 mW conduction loss at 2.8 A, critical for thermal budget in sealed enclosures. |
| VGS(th) | −0.47 to −0.9 V - Ensures full enhancement with 1.8 V GPIO; eliminates need for level-shifting in ultra-low-voltage MCU interfaces. |
| QG(tot) | 7.7 nC - Low total gate charge reduces driver power and enables fast 135 ns td(off) for high-frequency PWM control. |
| ID | −4.3 A (pulsed), −2.8 A continuous @ Tamb = 25 °C - Supports peak load currents in USB-C PD sink circuits and smart battery switches. |
| Ptot | 4165 mW @ Tsp = 25 °C - High solder-point power rating allows direct PCB copper pour mounting without heatsink. |
| Ciss | 744 pF - Input capacitance compatible with standard 50 Ω gate drivers; minimizes ringing in compact layouts. |
Pinout & Package
SOT23 (TO-236AB) plastic surface-mounted package: 3-pin, small-outline transistor with gull-wing leads; 2.8 mm × 1.4 mm footprint; drain-connected tab for thermal conduction to PCB copper.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | G (Gate) | Control terminal; accepts logic-level negative voltage to turn on; requires <100 nA leakage current handling. |
| 2 | S (Source) | Reference node for gate drive; connects to positive rail in high-side switch configuration; carries full load current. |
| 3 | D (Drain) | Power output terminal; thermally connected to PCB pad; must be routed with ≥6 cm² copper for 4.3 A pulsed operation. |
Key Features
| Feature | Design Value |
|---|---|
| Low threshold voltage | VGS(th) down to −0.47 V enables direct drive from 1.8 V microcontrollers without external biasing. |
| Trench MOSFET architecture | Delivers 58 mΩ RDS(on) in SOT23-2× lower than planar equivalents at same voltage rating and package size. |
| Optimized gate charge | QGD/QG(tot) ratio of 21% ensures clean Miller plateau transition and robust EMI performance in SMPS. |
| Enhanced thermal performance | Rth(j-sp) = 25 K/W with 6 cm² drain pad allows 2.8 A continuous current at 100 °C ambient without derating. |
| Integrated body diode | VSD = −1.2 V max at −0.9 A supports reverse-current blocking in battery backup paths without external diode. |
Applications
| Battery-Powered Portable Equipment | Load Switching in Wearables |
|---|---|
|
Use Scenario: Power sequencing and rail isolation in Bluetooth earbuds with dual-cell Li-ion input and 3.3 V/1.2 V LDOs. IC Role / Device Role / Timing Role: P-channel high-side load switch controlling 3.3 V domain; turned on/off by baseband SoC GPIO. Use Value: Sub-1 V VGS(th) ensures full enhancement at 1.8 V GPIO; 74 mΩ RDS(on) limits dropout to <210 mV at 2.8 A peak load. |
Use Scenario: Dynamic power gating of sensor clusters (accelerometer, gyroscope, HRM) in fitness trackers. IC Role / Device Role / Timing Role: Low-quiescent-load power switch enabling <1 µA off-state leakage per channel. Use Value: −1 µA IDSS at 25 °C and −100 µA at 150 °C maintains system sleep current below 5 µA across temperature. |
| Low-Power DC-DC Converters | Battery Management Systems |
|
Use Scenario: Synchronous rectifier in 3.3 V buck converter supplying RF transceiver in LPWA modules. IC Role / Device Role / Timing Role: Secondary-side switch replacing Schottky diode; driven by controller's complementary output. Use Value: 18 ns rise time and 68 ns fall time support >2 MHz switching; 744 pC Ciss minimizes gate drive losses. |
Use Scenario: Reverse-polarity protection and charge/discharge path control in 2S Li-ion power banks. IC Role / Device Role / Timing Role: Back-to-back P-MOSFET pair (with companion N-MOS) for bidirectional current blocking. Use Value: −20 V VDS withstands 8.4 V fully charged 2S stack plus transient spikes; 16 A IDM handles short-circuit events. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar P-channel MOSFET applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| DMN2020LFG-7 | RDS(on) = 42 mΩ @ VGS = −4.5 V but VGS(th) = −1.0 V min - requires ≥2.5 V gate drive. | Better conduction efficiency above 3.3 V logic, but incompatible with 1.8 V MCUs. | Select when system uses 3.3 V GPIO and prioritizes lowest RDS(on) over gate drive simplicity. |
| SI2301DDS-T1-BE3 | VGS(th) = −0.4 V min, RDS(on) = 115 mΩ @ −4.5 V - higher on-resistance but wider threshold distribution. | Acceptable for ≤1.5 A loads where gate drive margin is critical and thermal headroom exists. | Choose for cost-sensitive designs with relaxed power loss targets and 1.8 V–2.5 V control rails. |
Compared with DMN2020LFG-7 and SI2301DDS-T1-BE3, PMV65XPVL uniquely balances sub-1 V threshold, 74 mΩ on-resistance, and 7.7 nC gate charge in SOT23-making it optimal for 1.8 V–3.3 V battery-powered systems requiring both low drive voltage and moderate current capability.
Availability
PMV65XPVL is available at Aetrix Electronics and suitable for battery management, wearable load switching, and low-power DC-DC converter designs requiring stable component supply and long-term industrial availability.
Supply support for PMV65XPVL includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert delivering high-performance, reliable discrete, logic, and MOSFET solutions with focus on efficiency, miniaturization, and automotive-grade quality.
PMV65XPVL belongs to Nexperia's TrenchMOS P-channel portfolio, engineered specifically for space-constrained, battery-operated consumer and industrial applications demanding low-threshold, low-RDS(on) switching in ultra-small packages.
FAQ
What is the maximum continuous drain current for PMV65XPVL at 100 °C ambient temperature?
The PMV65XPVL supports −1.8 A continuous drain current at Tamb = 100 °C with standard FR4 PCB mounting (single-sided copper, 6 cm² drain pad). This value is derived from the normalized current derating curve (Figure 2) and confirmed in Table 5 Limiting Values, where ID is specified as −1.8 A under those exact conditions.
Does PMV65XPVL have avalanche rating or UIS capability?
No, the official Nexperia datasheet for PMV65XPVL does not specify Unclamped Inductive Switching (UIS) energy rating, avalanche voltage, or repetitive avalanche characteristics. The device is characterized only for linear and switching operation within absolute maximum ratings; design-in for inductive load switching requires external clamping or snubbing.
Can PMV65XPVL be used in a high-side switch configuration with 5 V gate drive?
Yes-applying −5 V to the gate relative to source fully enhances the device, yielding RDS(on) ≤58 mΩ. However, since it is a P-channel MOSFET, high-side switching requires the source tied to the input rail (e.g., battery+), and gate driven negative relative to source; a level-shifter or charge pump is needed if controlling from a 0–5 V logic signal referenced to ground.
What is the thermal resistance from junction to solder point (Rth(j-sp)) for PMV65XPVL under standard PCB layout?
Rth(j-sp) is 25–30 K/W when mounted on an FR4 PCB with single-sided copper, tin-plated, and a 6 cm² mounting pad for the drain terminal (per Table 6). This value assumes the drain pad is directly connected to internal or external copper planes and reflects typical thermal performance in production-level reflow assembly.
PMV65XPVL Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- -
- Package/Case:
- TO-236-3, SC-59, SOT-23-3
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- FET Type:
- P-Channel
- Technology:
- MOSFET (Metal Oxide)
- Drain to Source Voltage (Vdss):
- 20 V
- Current - Continuous Drain (Id) @ 25°C:
- 2.8A (Ta)
- Drive Voltage (Max Rds On, Min Rds On):
- 1.8V, 4.5V
- Rds On (Max) @ Id, Vgs:
- 74mOhm @ 2.8A, 4.5V
- Vgs(th) (Max) @ Id:
- 900mV @ 250µA
- Gate Charge (Qg) (Max) @ Vgs:
- 7.7 nC @ 4 V
- Vgs (Max):
- ±12V
- Input Capacitance (Ciss) (Max) @ Vds:
- 744 pF @ 20 V
- FET Feature:
- -
- Power Dissipation (Max):
- 480mW (Ta)
- Operating Temperature:
- -55°C ~ 150°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- TO-236AB
PMV65XPVL FAQ
1.How can I place an order for PMV65XPVL through Aetrix?
Please submit a Request for Quotation (RFQ) for PMV65XPVL on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PMV65XPVL reliable?
The price and inventory of PMV65XPVL are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PMV65XPVL is usually 5 days.
3.What payment methods are accepted for PMV65XPVL?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PMV65XPVL transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PMV65XPVL?
PMV65XPVL orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PMV65XPVL order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PMV65XPVL?
For technical support, including PMV65XPVL datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PMV65XPVL requirements.
6.How does Aetrix verify that PMV65XPVL is sourced from the original manufacturer or authorized distributors?
All PMV65XPVL products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PMV65XPVL meets industry standards.
7.What is the process for return or replacement of PMV65XPVL?
All PMV65XPVL units undergo pre-shipment inspection (PSI). If there is an issue with PMV65XPVL, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PMV65XPVL part is unused and in its original packaging.
Return procedure for PMV65XPVL:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
PMV65XPVL Tags

-
BSZ180P03NS3EGATMA1
Infineon Technologies

-
SIRA14DP-T1-GE3
Vishay Siliconix

-
AO4419
Alpha & Omega Semiconductor Inc.

-
SISA14BDN-T1-GE3
Vishay Siliconix

-
PSMN9R5-30YLC,115
Nexperia USA Inc.

-
BUK9Y21-40E,115
Nexperia USA Inc.

-
RTQ035N03HZGTR
Rohm Semiconductor

-
FDMS7680
onsemi

-
RQ3E180BNTB
Rohm Semiconductor

-
STL6N2VH5
STMicroelectronics

-
DMPH4029LFGQ-7
Diodes Incorporated

-
DMT6015LSS-13
Diodes Incorporated
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

