Nexperia USA Inc. PSMN004-60B,118
- Part No.:
- PSMN004-60B,118
- Manufacturer:
- Nexperia USA Inc.
- Category:
- FETs, MOSFETs
- Package:
- TO-263-3, D2PAK (2 Leads + Tab), TO-263AB
- Datasheet:
-
PSMN004-60B,118.pdf
- Description:
- MOSFET N-CH 60V 75A D2PAK
- Quantity:
- Payment:

- Shipping:

Inventory:4,800
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Product details
Overview
PSMN004-60B from Nexperia is a standard-level N-channel TrenchMOS power MOSFET in D2PAK (SOT404) package, designed for high-efficiency DC-DC conversion and OR-ing circuits. It delivers 75 A continuous drain current at 10 V gate drive, 3.1 mΩ typical RDS(on) at 25 °C, and 60 V drain-source breakdown voltage - optimized for computing and industrial power stages.
For engineers reviewing the PSMN004-60B datasheet, PSMN004-60B pinout, PSMN004-60B application, or PSMN004-60B equivalent, key selection criteria include thermal resistance (0.65 K/W junction-to-mounting-base), fast switching (74 ns rise time, 54 nC QGD), avalanche ruggedness (500 mJ unclamped), and mounting-base–integrated drain connection for low-inductance PCB layout.
Technical Context
This device uses TrenchMOS silicon technology to achieve low conduction loss and high-frequency switching capability. Its gate threshold voltage ranges from 1 V at 175 °C to 4.4 V at –55 °C, enabling stable turn-on across wide temperature ranges while maintaining robust noise immunity at 20 V maximum gate-source rating.
The integrated mounting base serves as both mechanical heatsink interface and electrical drain terminal, reducing thermal impedance and parasitic inductance. Dynamic parameters - including 168 nC total gate charge and 8300 pF input capacitance - are characterized at 48 V VDS, 75 A ID, and 25 °C junction temperature for realistic synchronous buck stage modeling.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VDS | 60 V - Maximum blocking voltage for 48 V bus applications with margin against transients |
| RDS(on) | 3.1 mΩ typ @ 10 V, 25 A, 25 °C - Enables <1 W conduction loss at 50 A in high-current VRMs |
| ID | 75 A continuous @ Tmb = 25 °C - Supports high-density CPU/GPU power delivery without forced air |
| QGD | 54 nC - Low gate-drain charge minimizes Miller-induced switching delay in hard-switched topologies |
| Rth(j-mb) | 0.65 K/W - Enables direct copper-plate thermal coupling for >150 W dissipation with 100 °C ΔT |
| EAS | 500 mJ unclamped avalanche energy - Withstands single-event inductive turn-off stress in OR-ing and hot-swap circuits |
Pinout & Package
PSMN004-60B uses the SOT404 (D2PAK) plastic surface-mount package with a thermally enhanced mounting base electrically connected to the drain. Pin 2 is internally connected to the mounting base and not externally accessible; only pins 1 (Gate), 3 (Source), and the base (Drain) form the functional terminals.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| Pin 1 | Gate (G) | Control terminal; accepts 0–20 V drive; requires ≥10 V for full enhancement and minimal RDS(on) |
| Pin 3 | Source (S) | Reference node for gate drive and current sensing; forms low-impedance return path in high-side configurations |
| Mounting Base | Drain (D) | Primary power terminal and thermal interface; must be soldered to large copper area for thermal performance |
Key Features
| Feature | Design Value |
|---|---|
| Low RDS(on) | 3.1 mΩ typ enables <0.8 W conduction loss at 50 A, reducing thermal load in compact VRMs |
| Fast switching | 74 ns rise time + 75 ns fall time supports >500 kHz operation in high-efficiency DC-DC converters |
| TrenchMOS architecture | Optimized cell pitch and trench depth reduce gate charge and output capacitance vs planar MOSFETs |
| Mounting-base drain | Eliminates bond wire inductance and improves thermal path - critical for high di/dt OR-ing applications |
Applications
| Server VRM Phase Legs | OR-ing Diode Replacement |
|---|---|
Use Scenario: High-current, multi-phase buck converter supplying modern CPUs/GPUs on server motherboards. IC Role / Device Role / Timing Role: Low-side synchronous rectifier in 48 V–1 V conversion stages, operating at 300–600 kHz. Use Value: 3.1 mΩ RDS(on) reduces conduction loss by >40% versus older 5 mΩ MOSFETs, improving efficiency at 50–100 A loads. |
Use Scenario: Redundant 12 V power supply backplane where two supplies feed a common rail. IC Role / Device Role / Timing Role: Active OR-ing switch replacing Schottky diodes to minimize forward voltage drop and heat generation. Use Value: 0.8 V source-drain diode forward voltage at 25 A enables >99% efficiency vs 0.45 V diode drop - cutting thermal design overhead. |
| Industrial DC-DC Modules | Hot-Swap Controllers |
Use Scenario: Isolated 48 V input to 5/3.3 V non-isolated DC-DC modules in factory automation equipment. IC Role / Device Role / Timing Role: Primary switch in secondary-side synchronous rectification, handling up to 75 A continuous output. Use Value: 0.65 K/W Rth(j-mb) allows direct thermal coupling to chassis, eliminating need for external heatsinks in sealed enclosures. |
Use Scenario: Inrush current limiting and fault isolation in modular telecom shelf power distribution. IC Role / Device Role / Timing Role: Main pass element controlled by hot-swap IC to manage turn-on slew rate and overcurrent shutdown. Use Value: 400 A peak drain current and 500 mJ avalanche energy withstand transient faults during live insertion without failure. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar N-channel power MOSFET applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| IRF1404PBF | RDS(on) = 4.0 mΩ @ 10 V, 75 A; higher QG (131 nC); TO-220 package | Larger footprint and higher thermal resistance (1.5 K/W j-case) limits high-frequency density | Prefer when legacy TO-220 layout exists and switching frequency <200 kHz |
| STP75NF75 | RDS(on) = 12.5 mΩ @ 10 V, 75 A; lower VDS (75 V); TO-220FP package | Higher conduction loss increases thermal stress above 30 A; unsuitable for high-current VRMs | Acceptable only for lower-current (<20 A), cost-sensitive industrial SMPS |
Compared with IRF1404PBF and STP75NF75, PSMN004-60B delivers superior power density via D2PAK mounting-base thermal interface and lowest RDS(on) in its class - making it optimal for space-constrained, high-efficiency computing and OR-ing designs where thermal management and switching speed are critical.
Availability
PSMN004-60B is available at Aetrix Electronics and suitable for server motherboard VRMs, redundant power OR-ing circuits, and industrial DC-DC modules requiring stable component supply and long-term lifecycle support.
Supply support for PSMN004-60B includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on high-volume, high-reliability discrete, logic, and MOSFET solutions - spun off from NXP in 2017 and headquartered in Nijmegen, Netherlands.
This device belongs to the SiliconMAX standard-level TrenchMOS family, engineered specifically for high-current, high-frequency power conversion in computing, communications, and industrial systems - balancing low RDS(on), fast switching, and ruggedness.
FAQ
What is the maximum safe operating temperature for PSMN004-60B?
The absolute maximum junction temperature is 175 °C, and storage temperature range is –55 °C to +175 °C. For reliable long-term operation, keep Tj ≤150 °C under steady-state conditions using the provided thermal derating curves. The mounting base temperature (Tmb) must stay ≤100 °C to sustain 75 A continuous current per Figure 1.
Can PSMN004-60B be used in a high-side configuration?
Yes - it is an N-channel MOSFET and can operate in high-side topology when driven with a bootstrap or isolated gate driver that provides gate voltage ≥10 V above the source (drain rail). Its 20 V maximum VGS rating and 60 V VDS support use in 48 V systems with appropriate gate control.
Does the mounting base require electrical isolation from the PCB?
No - the mounting base is electrically connected to the drain (Pin 2), so it must be routed to the drain net on the PCB. Thermal interface material is not required if soldered directly to a large copper pour; however, electrical isolation is only needed if the drain potential differs from the PCB ground plane.
Is avalanche capability rated for repetitive operation?
No - the 500 mJ EAS rating is for non-repetitive, unclamped inductive switching events only. Repetitive avalanche operation is not specified or guaranteed; system design must avoid repeated exposure through proper snubbing, clamping, or layout to prevent cumulative junction damage.
PSMN004-60B,118 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- TrenchMOS™
- Package/Case:
- TO-263-3, D2PAK (2 Leads + Tab), TO-263AB
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- FET Type:
- N-Channel
- Technology:
- MOSFET (Metal Oxide)
- Drain to Source Voltage (Vdss):
- 60 V
- Current - Continuous Drain (Id) @ 25°C:
- 75A (Tc)
- Drive Voltage (Max Rds On, Min Rds On):
- 10V
- Rds On (Max) @ Id, Vgs:
- 3.6mOhm @ 25A, 10V
- Vgs(th) (Max) @ Id:
- 4V @ 1mA
- Gate Charge (Qg) (Max) @ Vgs:
- 168 nC @ 10 V
- Vgs (Max):
- ±20V
- Input Capacitance (Ciss) (Max) @ Vds:
- 8300 pF @ 25 V
- FET Feature:
- -
- Power Dissipation (Max):
- 230W (Tc)
- Operating Temperature:
- -55°C ~ 175°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- D2PAK
PSMN004-60B,118 FAQ
1.How can I place an order for PSMN004-60B,118 through Aetrix?
Please submit a Request for Quotation (RFQ) for PSMN004-60B,118 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
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6.How does Aetrix verify that PSMN004-60B,118 is sourced from the original manufacturer or authorized distributors?
All PSMN004-60B,118 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PSMN004-60B,118 meets industry standards.
7.What is the process for return or replacement of PSMN004-60B,118?
All PSMN004-60B,118 units undergo pre-shipment inspection (PSI). If there is an issue with PSMN004-60B,118, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PSMN004-60B,118 part is unused and in its original packaging.
Return procedure for PSMN004-60B,118:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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