Nexperia USA Inc. PSMN005-75B,118
- Part No.:
- PSMN005-75B,118
- Manufacturer:
- Nexperia USA Inc.
- Category:
- FETs, MOSFETs
- Package:
- TO-263-3, D2PAK (2 Leads + Tab), TO-263AB
- Datasheet:
-
PSMN005-75B,118.pdf
- Description:
- MOSFET N-CH 75V 75A D2PAK
- Quantity:
- Payment:

- Shipping:

Inventory:6,967
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
PSMN005-75B from Nexperia is a standard-level N-channel TrenchMOS power MOSFET in D2PAK (SOT404) package, designed for high-current DC-DC conversion and OR-ing functions. It delivers 75 V drain-source voltage rating, 75 A continuous drain current at Tmb = 25 °C, and ultra-low 4.3 mΩ RDS(on) at VGS = 10 V and Tj = 25 °C-enabling efficient power delivery in computing motherboard VRMs.
For engineers reviewing the PSMN005-75B datasheet, PSMN005-75B pinout, PSMN005-75B application, or PSMN005-75B equivalent, this device is selected for high-frequency switching topologies requiring low conduction loss, fast turn-on/turn-off (td(on) = 37 ns, tf = 74 ns), and robust avalanche energy handling (500 mJ).
Technical Context
This MOSFET employs TrenchMOS silicon technology to achieve optimized trade-offs between RDS(on), gate charge (QG(tot) = 165 nC), and output capacitance (Coss = 920 pF). Its gate threshold voltage (VGS(th)) ranges from 2–4 V at 25 °C, ensuring reliable enhancement-mode operation with standard 10 V gate drive.
The device features an integrated body diode with VSD = 0.8–1.2 V at IS = 25 A and exhibits unclamped avalanche ruggedness up to 500 mJ-critical for hard-switched synchronous buck stages and hot-swap OR-ing circuits where transient overvoltage events occur.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VDS | 75 V maximum - supports 48 V input bus architectures with 50 % derating margin |
| RDS(on) | 4.3 mΩ typical at VGS = 10 V, ID = 25 A, Tj = 25 °C - minimizes I²R conduction loss in high-current phases |
| ID | 75 A continuous at Tmb = 25 °C - enables single-device use in 50–60 A per-phase VRM designs |
| QGD | 50 nC typical - limits Miller-induced switching delay and improves controllability in high-dV/dt environments |
| Rth(j-mb) | 0.65 K/W - enables direct mounting to copper heatsink pads for thermal management without forced airflow |
| EAS | 500 mJ non-repetitive avalanche energy - sustains short-circuit events in unclamped inductive switching |
| Ciss | 8250 pF typical - impacts gate driver sizing and influences EMI profile in MHz-range switching |
Pinout & Package
PSMN005-75B uses the SOT404 (D2PAK) plastic surface-mount package with three leads: Gate (pin 1), Drain (pin 2, internally connected to mounting base), and Source (pin 3). Pin 2 is not externally accessible-drain connection is made via the exposed metal pad on the underside of the package.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (G) | Gate terminal | Controls channel conduction; requires ≤20 V gate drive; QG(tot) = 165 nC defines driver current demand |
| 2 (D) | Drain terminal (internal) | Electrically tied to mounting base; provides primary heat path and high-current return; no external lead |
| 3 (S) | Source terminal | Reference node for gate drive and current sensing; connects to low-side shunt or controller feedback |
Key Features
| Feature | Design Value |
|---|---|
| Ultra-low RDS(on) | 4.3 mΩ @ 10 V drives - reduces conduction loss by >30 % vs. comparable 5–6 mΩ MOSFETs in 50 A phase legs |
| TrenchMOS architecture | Enables <100 ns total switching time (td(on) + tr + td(off) + tf = 328 ns) - supports >1 MHz VRM operation |
| Robust avalanche rating | 500 mJ EAS - eliminates need for external clamping in synchronous rectifier failure scenarios |
| Thermal performance | 0.65 K/W Rth(j-mb) - allows 150 W dissipation at ΔT = 100 K with minimal heatsink area |
| Body diode VSD | 0.8–1.2 V @ 25 A - lowers reverse recovery loss during dead-time conduction in synchronous buck converters |
Applications
| Server VRM Phase Legs | OR-ing Diode Replacement |
|---|---|
|
Use Scenario: High-density 48 V-to-1 V server CPU VRM with multi-phase interleaving and >50 A per phase. IC Role / Device Role / Timing Role: Low-side synchronous rectifier switch operating at 500 kHz–1 MHz with precise gate timing control. Use Value: 4.3 mΩ RDS(on) cuts conduction loss by ~1.2 W per phase versus 6 mΩ alternatives, improving full-load efficiency by 0.4–0.6 %. |
Use Scenario: Dual 12 V power supply redundancy in telecom line cards, requiring automatic failover without reverse current. IC Role / Device Role / Timing Role: Active OR-ing switch controlled by dedicated ideal diode controller (e.g., LTC4359). Use Value: 75 A rating and 500 mJ avalanche capability enable safe hot-swap insertion and tolerate bus transients up to 75 V without latch-up. |
| High-Frequency DC-DC Converters | Industrial Motor Drive Half-Bridge |
|
Use Scenario: Compact 24 V input, 5 V/20 A isolated DC-DC module for FPGA power sequencing. IC Role / Device Role / Timing Role: Primary-side synchronous rectifier in active clamp forward topology with 1 MHz switching. Use Value: Fast 74 ns fall time and low Coss reduce switching loss by 22 % compared to TO-220 equivalents, enabling smaller magnetics. |
Use Scenario: 24–48 V BLDC motor drive half-bridge stage in factory automation controllers. IC Role / Device Role / Timing Role: Low-side switch in 3-phase inverter leg, driven by isolated gate driver with 6 Ω external resistance. Use Value: 400 A peak drain current rating supports 3× motor stall current surges; 175 °C max junction temperature ensures reliability under ambient 85 °C conditions. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar N-channel power MOSFET applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| IRF1405PBF | RDS(on) = 5.3 mΩ @ 10 V; TO-220 package; higher Rth(j-a) = 62 K/W | Limited to lower-frequency (<300 kHz) and lower-current (<50 A) designs due to thermal and conduction constraints | Choose when board space permits through-hole mounting and cost sensitivity outweighs efficiency gains |
| IXFH75N10P | RDS(on) = 10.5 mΩ @ 10 V; TO-247 package; higher QG = 220 nC | Requires stronger gate driver; unsuitable for >500 kHz operation due to slower switching and higher losses | Prefer only if legacy PCB layout mandates TO-247 footprint and 100 V rating is mandatory |
Compared with IRF1405PBF and IXFH75N10P, PSMN005-75B offers superior thermal coupling (0.65 K/W vs. >1.0 K/W), 15–20 % lower RDS(on), and faster switching-making it optimal for compact, high-efficiency, high-frequency power stages where D2PAK mounting is acceptable.
Availability
PSMN005-75B is available at Aetrix Electronics and suitable for server VRM design, telecom OR-ing systems, and industrial DC-DC converter development requiring stable component supply and long-term production continuity.
Supply support for PSMN005-75B includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert specializing in high-volume, high-reliability discrete and logic devices, with roots in Philips Semiconductors and headquartered in Nijmegen, Netherlands.
This device belongs to the SiliconMAX standard-level TrenchMOS family-engineered for mainstream power conversion in computing, communications, and industrial equipment where efficiency, thermal performance, and ruggedness are prioritized over ultra-low-voltage operation.
FAQ
What is the maximum allowable gate-source voltage for PSMN005-75B?
The absolute maximum VGS is ±20 V under steady-state conditions, with a pulsed peak rating of ±30 V (tp ≤ 50 µs, duty cycle ≤ 25 %). Exceeding ±20 V continuously risks gate oxide degradation; Nexperia recommends limiting drive to 12–15 V for long-term reliability and noise immunity in high-dV/dt environments.
Can PSMN005-75B be used in linear mode (as a pass transistor)?
No-it is not characterized or qualified for linear (saturation) operation. The Safe Operating Area (SOA) curve in Figure 3 shows limited DC capability beyond 10 V VDS, and thermal runaway risk increases rapidly above Tj = 125 °C in linear mode. This device is intended strictly for switched-mode applications with defined duty cycles and adequate heatsinking.
Is the drain electrically connected to the mounting base?
Yes-pin 2 (drain) is internally bonded to the exposed metal pad on the underside of the D2PAK package, which serves as both the primary electrical connection and thermal path. This pad must be soldered to a large copper area or heatsink; isolation from chassis ground is required unless system topology explicitly references drain to ground.
What is the typical body diode reverse recovery charge (Qrr)?
The datasheet does not specify Qrr or trr; only VSD = 0.8–1.2 V at IS = 25 A is provided. For synchronous rectification, designers should rely on measured waveforms or application notes (e.g., Nexperia AN11158) and assume soft recovery behavior typical of TrenchMOS body diodes-avoiding hard commutation into the diode without snubbing.
PSMN005-75B,118 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- TrenchMOS™
- Package/Case:
- TO-263-3, D2PAK (2 Leads + Tab), TO-263AB
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Last Time Buy
- FET Type:
- N-Channel
- Technology:
- MOSFET (Metal Oxide)
- Drain to Source Voltage (Vdss):
- 75 V
- Current - Continuous Drain (Id) @ 25°C:
- 75A (Tc)
- Drive Voltage (Max Rds On, Min Rds On):
- 10V
- Rds On (Max) @ Id, Vgs:
- 5mOhm @ 25A, 10V
- Vgs(th) (Max) @ Id:
- 4V @ 1mA
- Gate Charge (Qg) (Max) @ Vgs:
- 165 nC @ 10 V
- Vgs (Max):
- ±20V
- Input Capacitance (Ciss) (Max) @ Vds:
- 8250 pF @ 25 V
- FET Feature:
- -
- Power Dissipation (Max):
- 230W (Tc)
- Operating Temperature:
- -55°C ~ 175°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- D2PAK
PSMN005-75B,118 FAQ
1.How can I place an order for PSMN005-75B,118 through Aetrix?
Please submit a Request for Quotation (RFQ) for PSMN005-75B,118 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PSMN005-75B,118 reliable?
The price and inventory of PSMN005-75B,118 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PSMN005-75B,118 is usually 5 days.
3.What payment methods are accepted for PSMN005-75B,118?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PSMN005-75B,118 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PSMN005-75B,118?
PSMN005-75B,118 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PSMN005-75B,118 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PSMN005-75B,118?
For technical support, including PSMN005-75B,118 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PSMN005-75B,118 requirements.
6.How does Aetrix verify that PSMN005-75B,118 is sourced from the original manufacturer or authorized distributors?
All PSMN005-75B,118 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PSMN005-75B,118 meets industry standards.
7.What is the process for return or replacement of PSMN005-75B,118?
All PSMN005-75B,118 units undergo pre-shipment inspection (PSI). If there is an issue with PSMN005-75B,118, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PSMN005-75B,118 part is unused and in its original packaging.
Return procedure for PSMN005-75B,118:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
PSMN005-75B,118 Tags

-
BSZ180P03NS3EGATMA1
Infineon Technologies

-
SIRA14DP-T1-GE3
Vishay Siliconix

-
AO4419
Alpha & Omega Semiconductor Inc.

-
SISA14BDN-T1-GE3
Vishay Siliconix

-
PSMN9R5-30YLC,115
Nexperia USA Inc.

-
BUK9Y21-40E,115
Nexperia USA Inc.

-
RTQ035N03HZGTR
Rohm Semiconductor

-
FDMS7680
onsemi

-
RQ3E180BNTB
Rohm Semiconductor

-
STL6N2VH5
STMicroelectronics

-
DMPH4029LFGQ-7
Diodes Incorporated

-
DMT6015LSS-13
Diodes Incorporated
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

