Nexperia USA Inc. PSMN006-20K,518
- Part No.:
- PSMN006-20K,518
- Manufacturer:
- Nexperia USA Inc.
- Category:
- FETs, MOSFETs
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
PSMN006-20K,518.pdf
- Description:
- MOSFET N-CH 20V 32A 8SO
- Quantity:
- Payment:

- Shipping:

Inventory:5,866
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
PSMN006-20K from Nexperia is an N-channel TrenchMOS silicon power MOSFET in SO8 (SOT96-1) package, designed for ultra-low-level gate drive applications. It features 4.2 mΩ RDS(on) at VGS = 4.5 V, 20 V VDS, and 32 A continuous drain current - optimized for high-efficiency DC-DC converters and motherboard VRMs.
For engineers reviewing the PSMN006-20K datasheet, PSMN006-20K pinout, PSMN006-20K application, or PSMN006-20K equivalent, this device is selected for low-voltage, high-current switching where gate drive voltage is constrained to ≤2.5 V and on-resistance stability across temperature is critical.
Technical Context
This MOSFET employs TrenchMOS technology with SiliconMAX architecture to achieve sub-5 mΩ on-resistance at 4.5 V gate drive while maintaining robust threshold voltage control (VGS(th) = 0.4–0.7 V at 25 °C). Its low QGD (13.2 nC) and fast switching (tr = 32 ns, tf = 90 ns) support high-frequency synchronous rectification.
The device integrates a source-drain diode with 0.75–1.3 V forward voltage at 3 A and 47 ns reverse recovery time, enabling efficient body-diode conduction during dead-time intervals in buck converters and half-bridge topologies.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VDS | 20 V - Maximum blocking voltage compatible with 12 V input rails and transient margin in point-of-load converters. |
| RDS(on) @ 4.5 V | 4.2–5.0 mΩ - Enables ≤120 mW conduction loss at 5 A, critical for thermally constrained motherboard layouts. |
| ID continuous | 32 A @ Tsp = 25 °C - Supports high-current CPU/GPU VRM phases when mounted on metal-clad PCBs. |
| QGD | 13.2 nC - Low gate-drain charge minimizes Miller-induced switching delay and improves controllability in hard-switched topologies. |
| Rth(j-sp) | 15 K/W - Thermal resistance from junction to solder point enables direct thermal coupling to copper pour for passive cooling. |
| VGS(th) | 0.4–0.7 V @ 25 °C - Ensures reliable turn-on with logic-level drivers (e.g., 1.8 V/2.5 V microcontroller GPIO). |
| Ciss | 4350 pF - Input capacitance impacts gate driver sizing and influences EMI behavior in MHz-range switching. |
Pinout & Package
PSMN006-20K uses the SOT96-1 (SO8) plastic small outline package with 3.9 mm body width and exposed drain paddle for thermal enhancement. The 8-pin layout supports high-current routing with parallel source and drain terminals.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 2, 3 | Source (S) | Three parallel source pins reduce bond-wire inductance and improve current sharing in high-dI/dt applications. |
| 4 | Gate (G) | Single gate terminal with low-input capacitance design; requires <6 Ω external gate resistor for optimal switching. |
| 5, 6, 7, 8 | Drain (D) | Four parallel drain pins connected to internal power die paddle - optimized for thermal dissipation and low-inductance output paths. |
Key Features
| Feature | Design Value |
|---|---|
| Ultra-low RDS(on) at 1.8 V drive | 5.7–8.2 mΩ - Enables operation with next-generation low-voltage controllers without gate boosting. |
| TrenchMOS SiliconMAX architecture | Optimized cell pitch and trench depth - delivers best-in-class RDS(on) × QG figure of merit for 20 V class. |
| Low QGD/QG ratio | 13.2 nC / 32 nC = 41% - Reduces risk of false turn-on during high dV/dt commutation in synchronous rectifiers. |
| Robust body diode | trr = 47 ns, Qr = 17 nC - Minimizes reverse recovery losses in non-complementary switching stages. |
| Qualified for industrial temp range | Tj = −55 to 150 °C - Validated for sustained operation in server PSU and telecom base station environments. |
Applications
| Computer Motherboards | DC-to-DC Converters |
|---|---|
|
Use Scenario: Core voltage regulation for modern CPUs and GPUs using multiphase buck converters. IC Role / Device Role / Timing Role: High-side synchronous rectifier switch operating at 300–1000 kHz with 1.8 V gate drive. Use Value: 4.2 mΩ RDS(on) at 4.5 V reduces conduction loss by >18% versus legacy 6 mΩ devices, improving VRM efficiency at 30–60 A load points. |
Use Scenario: Secondary-side synchronous rectification in isolated 12 V → 3.3 V/5 V flyback or forward converters. IC Role / Device Role / Timing Role: Low-side switch controlled by transformer-coupled or opto-isolated gate driver. Use Value: 0.75 V VSD at 3 A lowers body-diode conduction loss by ~35% compared to standard Schottky solutions, reducing heat sink requirements. |
| Switched-Mode Power Supplies | Industrial Motor Control Modules |
|
Use Scenario: Primary-side high-frequency switching in compact AC-DC adapters and USB-PD power bricks. IC Role / Device Role / Timing Role: Low-voltage auxiliary rail switch in active clamp or resonant LLC secondary stage. Use Value: 15 K/W Rth(j-sp) allows direct mounting on 2 oz copper thermal pads, eliminating need for thermal vias in space-constrained designs. |
Use Scenario: H-bridge half-bridge leg in 24 V BLDC motor gate driver modules for factory automation. IC Role / Device Role / Timing Role: Low-side current-sense path switch with integrated Kelvin source connection capability. Use Value: Triple-source pin configuration enables accurate shunt-based current sensing with minimal offset error from parasitic bond wire resistance. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar N-channel low-voltage power MOSFET applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Infineon BSC010N04LS | RDS(on) = 1.0 mΩ @ 4.5 V (lower), but VDS = 40 V (higher voltage rating); SO8 package with different pinout (G-S-D-S-D-S-D-G). | Higher voltage margin suits 24 V systems; lower RDS(on) improves efficiency above 10 A but increases cost and gate charge (QG = 39 nC). | Select when system input exceeds 15 V or when <1 mΩ conduction loss justifies higher gate drive power and layout complexity. |
| ON Semiconductor NTMFS4C06NT1G | RDS(on) = 4.5 mΩ @ 4.5 V (similar), but uses PowerTrench® with 12 V VGS(max); SO8 with standard pinout (G-S-D-D-D-D-S-S). | Lower gate voltage rating limits compatibility with 12 V gate drivers; slightly higher QGD (15.5 nC) increases Miller susceptibility. | Prefer when existing designs use ON Semi ecosystem or require tighter VGS tolerance control under overvoltage transients. |
Compared with BSC010N04LS and NTMFS4C06NT1G, PSMN006-20K offers the lowest VGS(th) (0.4 V) and best RDS(on) stability below 2.5 V drive - making it uniquely suited for ultra-low-voltage controller interfaces without level-shifting circuitry.
Availability
PSMN006-20K is available at Aetrix Electronics and suitable for computer motherboards, DC-to-DC converters, and switched-mode power supplies requiring stable component supply and long-term industrial lifecycle support.
Supply support for PSMN006-20K includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on high-volume, high-reliability discrete, logic, and MOSFET solutions - with manufacturing rooted in process control and automotive-grade quality systems.
This device belongs to Nexperia's SiliconMAX ultra-low-level TrenchMOS family, engineered specifically for high-efficiency, low-voltage power conversion in computing and communications infrastructure where gate drive headroom is limited.
FAQ
What is the maximum safe operating junction temperature for PSMN006-20K?
The absolute maximum junction temperature is 150 °C per IEC 60134 limiting values. Continuous operation above 130 °C degrades RDS(on) performance and accelerates wear-out; derating curves in Figure 2 show usable power dissipation drops to 50% at Tsp = 100 °C on standard metal-clad boards.
Can PSMN006-20K be used with 1.8 V gate drive in production designs?
Yes - datasheet specifies RDS(on) = 5.7–8.2 mΩ at VGS = 1.8 V and ID = 5 A, with VGS(th) as low as 0.15 V at 150 °C. This enables direct interface with 1.8 V FPGA I/O banks and low-power microcontrollers without gate boosters.
Does PSMN006-20K have avalanche ruggedness rating?
No avalanche energy rating (EAS) is specified in the datasheet. The device is not characterized for repetitive unclamped inductive switching; external snubbers or clamping circuits are required in inductive load applications exceeding safe operating area limits shown in Figure 3.
How does the triple-source pin configuration affect PCB layout?
The three parallel source pins (pins 1–3) must be routed to a common low-impedance ground plane with equal-length traces to avoid current imbalance. Use thermal relief-free polygons and ≥0.5 mm trace width per pin to maintain <0.3 mΩ total source loop resistance at 32 A peak current.
PSMN006-20K,518 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- TrenchMOS™
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- FET Type:
- N-Channel
- Technology:
- MOSFET (Metal Oxide)
- Drain to Source Voltage (Vdss):
- 20 V
- Current - Continuous Drain (Id) @ 25°C:
- 32A (Tc)
- Drive Voltage (Max Rds On, Min Rds On):
- 1.8V, 4.5V
- Rds On (Max) @ Id, Vgs:
- 5mOhm @ 5A, 4.5V
- Vgs(th) (Max) @ Id:
- 700mV @ 1mA (Typ)
- Gate Charge (Qg) (Max) @ Vgs:
- 32 nC @ 2.5 V
- Vgs (Max):
- ±10V
- Input Capacitance (Ciss) (Max) @ Vds:
- 4350 pF @ 20 V
- FET Feature:
- -
- Power Dissipation (Max):
- 8.3W (Tc)
- Operating Temperature:
- -55°C ~ 150°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SO
PSMN006-20K,518 FAQ
1.How can I place an order for PSMN006-20K,518 through Aetrix?
Please submit a Request for Quotation (RFQ) for PSMN006-20K,518 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PSMN006-20K,518 reliable?
The price and inventory of PSMN006-20K,518 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PSMN006-20K,518 is usually 5 days.
3.What payment methods are accepted for PSMN006-20K,518?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PSMN006-20K,518 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PSMN006-20K,518?
PSMN006-20K,518 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PSMN006-20K,518 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PSMN006-20K,518?
For technical support, including PSMN006-20K,518 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PSMN006-20K,518 requirements.
6.How does Aetrix verify that PSMN006-20K,518 is sourced from the original manufacturer or authorized distributors?
All PSMN006-20K,518 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PSMN006-20K,518 meets industry standards.
7.What is the process for return or replacement of PSMN006-20K,518?
All PSMN006-20K,518 units undergo pre-shipment inspection (PSI). If there is an issue with PSMN006-20K,518, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PSMN006-20K,518 part is unused and in its original packaging.
Return procedure for PSMN006-20K,518:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
PSMN006-20K,518 Tags

-
BSZ180P03NS3EGATMA1
Infineon Technologies

-
SIRA14DP-T1-GE3
Vishay Siliconix

-
AO4419
Alpha & Omega Semiconductor Inc.

-
SISA14BDN-T1-GE3
Vishay Siliconix

-
PSMN9R5-30YLC,115
Nexperia USA Inc.

-
BUK9Y21-40E,115
Nexperia USA Inc.

-
RTQ035N03HZGTR
Rohm Semiconductor

-
FDMS7680
onsemi

-
RQ3E180BNTB
Rohm Semiconductor

-
STL6N2VH5
STMicroelectronics

-
DMPH4029LFGQ-7
Diodes Incorporated

-
DMT6015LSS-13
Diodes Incorporated
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

