Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Discrete Semiconductor Products > Transistors > FETs, MOSFETs > FETs, MOSFETs

Nexperia USA Inc. PSMN009-100B,118

Name: PSMN009-100B,118
Brand: Nexperia USA Inc.
SKU: PSMN009-100B,118
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: PSMN009-100B,118

Manufacturer:: Nexperia USA Inc.

Category:: FETs, MOSFETs

Package:: TO-263-3, D2PAK (2 Leads + Tab), TO-263AB

Datasheet:: PSMN009-100B,118.pdf

Description:: NEXPERIA PSMN009-100B - 75A, 100

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:3,463

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

PSMN009-100B,118 from Nexperia is a standard-level N-channel TrenchMOS power MOSFET in D2PAK (SOT404) package, rated for 100 V V_DS, 75 A continuous drain current at T_mb = 25 °C, and 7.5 mΩ R_DS(on) at V_GS = 10 V and T_j = 25 °C. It delivers low conduction loss and fast switching for high-frequency DC–DC converters on computing motherboards.

For engineers reviewing the PSMN009-100B,118 datasheet, PSMN009-100B,118 pinout, PSMN009-100B,118 application, or PSMN009-100B,118 equivalent, key selection criteria include its 0.65 K/W junction-to-mounting-base thermal resistance, 44 nC Q_GD, 156 nC Q_G(tot), avalanche energy rating of 120 mJ, and suitability for OR-ing and synchronous rectification in high-density power stages.

Technical Context

This MOSFET employs TrenchMOS silicon technology to achieve optimized trade-offs between R_DS(on), gate charge, and switching speed. Its 100 V breakdown voltage and 175 °C maximum junction temperature support robust operation in industrial and computing power rails.

The device features an integrated source-drain diode with 0.8–1.2 V forward voltage at 25 A and exhibits unclamped avalanche capability up to 120 mJ at 35 A, enabling reliable operation under transient overvoltage conditions without external snubbers.

Key Specifications

Parameter	Value and Actual Design Meaning
V_DS	100 V - Maximum drain-source blocking voltage; supports 48 V input bus designs with 2× safety margin.
R_DS(on)	7.5 mΩ (typ.) at V_GS = 10 V, I_D = 25 A, T_j = 25 °C - Enables <1.9 W conduction loss at 50 A, critical for thermally constrained PCB layouts.
Q_G(tot)	156 nC - Total gate charge determines driver strength requirement; compatible with common 1–2 A peak gate drivers.
Q_GD	44 nC - Gate-drain charge governs Miller plateau duration; enables clean turn-off in hard-switched topologies.
R_th(j-mb)	0.65 K/W - Junction-to-mounting-base thermal resistance allows direct heatsink mounting for >200 W dissipation with modest thermal interface.
E_AS	120 mJ - Non-repetitive avalanche energy rating permits safe operation during inductive switching transients without clamping circuits.
C_iss	8250 pF - Input capacitance impacts gate drive loop stability and EMI filter design in high-frequency (>500 kHz) converters.

Pinout & Package

PSMN009-100B,118 uses the SOT404 (D2PAK) plastic surface-mount package with exposed mounting base connected internally to the drain. The package features three leads (one cropped), optimized for high-current PCB mounting and thermal transfer via the metal base.

Pin/Terminal	Circuit Role	Design Meaning
1 (G)	Gate	Control terminal; requires ≥10 V drive for full enhancement; gate leakage <100 nA ensures low standby power.
2 (D)	Drain	Main high-side current path; electrically tied to mounting base; must be isolated from other copper planes except dedicated heatsink pad.
3 (S)	Source	Reference node for gate drive and current sensing; low-inductance connection essential for minimizing switching oscillation.

Key Features

Feature	Design Value
Low R_DS(on)	7.5 mΩ typ. at 25 °C enables high-efficiency synchronous rectification in 12 V/48 V output stages.
Fast switching	38 ns t_d(on), 120 ns t_d(off), and 43 ns t_f support >1 MHz converter operation with minimal dead-time loss.
TrenchMOS architecture	Optimized cell pitch and trench depth reduce gate charge while maintaining ruggedness and threshold stability across temperature.
Avalanche-rated	120 mJ E_AS allows reliable unclamped inductive switching in OR-ing and hot-swap applications without added protection.
Thermally enhanced D2PAK	0.65 K/W R_th(j-mb) enables >150 W continuous power dissipation with simple copper pour heatsinking.

Applications

Server VRM Phase Legs

OR-ing Diode Replacement

Use Scenario: High-current, multi-phase buck converters supplying CPU/GPU core voltage (0.8–1.8 V) in datacenter servers.

IC Role / Device Role / Timing Role: Low-side synchronous rectifier switch operating at 300–600 kHz with precise gate timing control.

Use Value: 7.5 mΩ R_DS(on) reduces conduction loss by >40% vs. legacy 12 mΩ devices, directly improving VRM efficiency and thermal headroom.

Use Scenario: Redundant 12 V power supply inputs in telecom line cards requiring automatic failover without reverse current.

IC Role / Device Role / Timing Role: Unidirectional power path controller replacing Schottky diodes in active OR-ing circuits.

Use Value: 0.8 V V_SD forward drop at 25 A cuts power loss by ~75% versus 0.45 V Schottky, enabling higher current density and lower board temperature.

Industrial DC–DC Converters

Motor Drive Half-Bridge Legs

Use Scenario: 24–48 V input, 5–24 V output isolated/non-isolated converters for PLCs and HMIs.

IC Role / Device Role / Timing Role: Primary-side high-side switch in hard-switched flyback or forward topologies.

Use Value: 100 V V_DS rating accommodates 40 V nominal bus with 25% surge margin; 175 °C T_j(max) ensures reliability in sealed enclosures.

Use Scenario: 24–48 V H-bridge motor drivers for BLDC fans and small actuators in factory automation.

IC Role / Device Role / Timing Role: Low-side switch in half-bridge configuration with bootstrap gate drive.

Use Value: 400 A pulsed I_DM supports high-torque startup surges; fast 59 ns t_r minimizes shoot-through risk during commutation.

Equivalent & Alternatives

The following parts are listed as comparable options for similar N-channel power MOSFET applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
IRF1404PBF	R_DS(on) = 4 mΩ (lower), but Q_G = 131 nC and no specified avalanche rating; TO-220 package limits thermal performance.	Lacks mounting-base thermal path; unsuitable for high-power density SMT designs requiring <1 K/W R_th.	Prefer when lowest R_DS(on) dominates and through-hole assembly is acceptable.
STP110N10F7	R_DS(on) = 9.5 mΩ (higher), Q_G = 110 nC (lower), 100 V rating, D²PAK package, 100% avalanche tested.	Higher R_DS(on) increases conduction loss; lower Q_G eases gate drive but sacrifices switching speed.	Prefer when guaranteed avalanche ruggedness is mandatory and 1.5 mΩ R_DS(on) penalty is acceptable.

Compared with IRF1404PBF and STP110N10F7, PSMN009-100B,118 offers the best balance of low R_DS(on), moderate Q_G, proven avalanche capability, and SMT-optimized thermal performance-making it ideal for space-constrained, high-efficiency computing and industrial power stages.

Availability

PSMN009-100B,118 is available at Aetrix Electronics and suitable for server VRMs, industrial DC–DC converters, and motor drive half-bridge legs requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for PSMN009-100B,118 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on high-volume, high-reliability discrete and logic components, with leadership in MOSFETs, ESD protection, and automotive-grade logic.

This part belongs to the SiliconMAX standard-level TrenchMOS family, engineered specifically for high-efficiency, high-frequency power conversion in computing, communications, and industrial infrastructure equipment.

FAQ

What is the maximum continuous drain current for PSMN009-100B,118 at 100 °C mounting base temperature?

The maximum continuous drain current is 65 A at T_mb = 100 °C, per Figure 1 in the datasheet. This derating reflects thermal limitations of the D2PAK package under real-world heatsink conditions and must be used-not the 75 A rating at 25 °C-for thermal design validation.

Does PSMN009-100B,118 require a negative gate voltage for safe turn-off in high-dV/dt environments?

No. The device has a gate threshold voltage range of 2–4 V at 25 °C and remains fully off with 0 V gate drive. Its V_GS rating of ±20 V allows use of simple 0–10 V or 0–12 V gate drivers without negative bias circuitry, simplifying layout and reducing BOM count.

Can PSMN009-100B,118 be used in linear mode (Ohmic region) for analog current regulation?

No. While it can conduct in the linear region, its Safe Operating Area (SOA) curve (Figure 3) shows severe pulse-width and voltage limitations below 10 V V_DS. It is not characterized or qualified for sustained linear-mode operation and lacks SOA guarantees beyond the 100 µs–10 ms pulsed region shown.

Is the mounting base electrically isolated from the drain terminal?

No. Pin 2 (drain) and the mounting base are internally connected and share the same electrical node. The datasheet explicitly states "mb: mounting base; connected to drain" in Table 2. PCB layout must treat the entire exposed copper pad as a high-voltage, high-current drain node with appropriate clearance and creepage.

PSMN009-100B,118 Specifications

Product attributes: Attribute value

Manufacturer:: Nexperia USA Inc.

Series:: TrenchMOS™

Package/Case:: TO-263-3, D2PAK (2 Leads + Tab), TO-263AB

Packaging:: Bulk

Product Status:: Active

FET Type:: N-Channel

Technology:: MOSFET (Metal Oxide)

Drain to Source Voltage (Vdss):: 100 V

Current - Continuous Drain (Id) @ 25°C:: 75A (Tc)

Drive Voltage (Max Rds On, Min Rds On):: 10V

Rds On (Max) @ Id, Vgs:: 8.8mOhm @ 25A, 10V

Vgs(th) (Max) @ Id:: 4V @ 1mA

Gate Charge (Qg) (Max) @ Vgs:: 156 nC @ 10 V

Vgs (Max):: ±20V

Input Capacitance (Ciss) (Max) @ Vds:: 8250 pF @ 25 V

FET Feature:: -

Power Dissipation (Max):: 230W (Tc)

Operating Temperature:: -55°C ~ 175°C (TJ)

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: D2PAK

PSMN009-100B,118 FAQ

1.How can I place an order for PSMN009-100B,118 through Aetrix?

Please submit a Request for Quotation (RFQ) for PSMN009-100B,118 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for PSMN009-100B,118 reliable?

The price and inventory of PSMN009-100B,118 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PSMN009-100B,118 is usually 5 days.

3.What payment methods are accepted for PSMN009-100B,118?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PSMN009-100B,118 transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for PSMN009-100B,118?

PSMN009-100B,118 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your PSMN009-100B,118 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for PSMN009-100B,118?

For technical support, including PSMN009-100B,118 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PSMN009-100B,118 requirements.

6.How does Aetrix verify that PSMN009-100B,118 is sourced from the original manufacturer or authorized distributors?

All PSMN009-100B,118 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PSMN009-100B,118 meets industry standards.

7.What is the process for return or replacement of PSMN009-100B,118?

All PSMN009-100B,118 units undergo pre-shipment inspection (PSI). If there is an issue with PSMN009-100B,118, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The PSMN009-100B,118 part is unused and in its original packaging.

Return procedure for PSMN009-100B,118:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-03 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-01 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

2026-08-21 What Is an LED Driver? Types, Circuits, Dimming, and Selection

An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…

2026-08-18 Operational Amplifier (Op Amp): Basics, Configurations, Feedback and Applications

Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

2026-08-14 Jumper Cables: How to Use, Connect and Choose Them Safely

Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…