Nexperia USA Inc. PSMN015-100B,118
- Part No.:
- PSMN015-100B,118
- Manufacturer:
- Nexperia USA Inc.
- Category:
- FETs, MOSFETs
- Package:
- TO-263-3, D2PAK (2 Leads + Tab), TO-263AB
- Datasheet:
-
PSMN015-100B,118.pdf
- Description:
- MOSFET N-CH 100V 75A D2PAK
- Quantity:
- Payment:

- Shipping:

Inventory:8,091
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
PSMN015-100B from Nexperia is a standard-level N-channel TrenchMOS power MOSFET in D2PAK (SOT404) package, rated for 100 V VDS, 75 A continuous drain current at Tmb = 25 °C, and 12 mΩ typical RDS(on) at VGS = 10 V and Tj = 25 °C. It features avalanche ruggedness (320 mJ unclamped), low gate charge (QG(tot) = 90 nC), and is qualified for computing, communications, consumer, and industrial DC-DC and SMPS applications.
For engineers reviewing the PSMN015-100B datasheet, PSMN015-100B pinout, PSMN015-100B application, or PSMN015-100B equivalent, key selection criteria include its 100 V blocking capability, thermal resistance of 0.5 K/W (junction-to-mounting base), avalanche energy rating, gate-drive compatibility with 10 V logic, and mounting-base–integrated drain connection for high-current PCB thermal management.
Technical Context
This device employs TrenchMOS silicon technology to achieve low on-resistance and fast switching performance. Its gate threshold voltage ranges from 2 V to 4 V at 25 °C, enabling reliable turn-on with standard 10 V gate drivers while maintaining low leakage (IDSS ≤ 10 µA at 25 °C). The integrated mounting base serves as both mechanical anchor and thermal path, directly connecting to the drain terminal.
Dynamic behavior is characterized by QGD = 35 nC and Ciss = 4900 pF at VDS = 25 V, supporting efficient hard-switching in high-frequency power converters. The source-drain diode exhibits VSD = 0.8–1.1 V at 25 A and trr = 80 ns, suitable for synchronous rectification and freewheeling roles where body-diode conduction occurs.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VDS | 100 V - Maximum drain-source blocking voltage; supports 48 V input bus designs with 2× safety margin. |
| RDS(on) | 12 mΩ (typ) @ VGS = 10 V, ID = 25 A, Tj = 25 °C - Enables <1.9 W conduction loss at 35 A, critical for high-efficiency power stages. |
| ID (cont) | 75 A @ Tmb = 25 °C - High current handling enabled by low RDS(on) and D2PAK thermal design. |
| EAS | 320 mJ (unclamped) - Confirmed avalanche energy rating ensures robustness against inductive switching transients. |
| QG(tot) | 90 nC - Total gate charge determines driver strength requirement; compatible with common 1–2 A peak gate drivers. |
| Rth(j-mb) | 0.5 K/W - Junction-to-mounting base thermal resistance enables direct heatsink coupling for >200 W dissipation capability. |
| tr/tf | 65 ns / 50 ns - Fast switching transitions reduce switching losses in 100–500 kHz SMPS topologies. |
Pinout & Package
PSMN015-100B uses the SOT404 (D2PAK) plastic surface-mount package with an exposed metal mounting base electrically connected to the drain. Pin 2 is internally connected to the mounting base and not externally accessible; only pins 1 (Gate), 3 (Source), and the mounting base (Drain) are functional terminals.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| Pin 1 | Gate (G) | Control terminal; requires 10 V drive for full enhancement; low input capacitance (Ciss = 4900 pF) eases driver design. |
| Pin 3 | Source (S) | Reference node for gate drive and current sensing; isolated from mounting base to enable high-side or low-side configuration. |
| Mounting Base (mb) | Drain (D) | Primary current and thermal path; must be soldered to large copper area or heatsink; electrically identical to internal drain node. |
Key Features
| Feature | Design Value |
|---|---|
| Low RDS(on) | 12 mΩ typ at 10 V drive reduces conduction loss by >30% vs. legacy planar MOSFETs in same package. |
| Avalanche ruggedness | 320 mJ non-repetitive EAS allows safe operation under inductive load switching without external snubbers. |
| TrenchMOS technology | Enables higher cell density and lower gate charge, improving figure-of-merit (RDS(on) × QG) by 2.2× over comparable planar devices. |
| Mounting base thermal path | 0.5 K/W Rth(j-mb) delivers >3× better thermal performance than junction-to-ambient (50 K/W), enabling compact high-power designs. |
Applications
| Server VRM Power Stage | Industrial DC-DC Converter |
|---|---|
|
Use Scenario: Primary switch in 48 V–12 V buck converter for CPU voltage regulation in data center servers. IC Role / Device Role / Timing Role: High-side synchronous rectifier switch operating at 300–600 kHz with 10 V gate drive. Use Value: 12 mΩ RDS(on) and 90 nC QG minimize combined conduction and switching losses, achieving >95% efficiency at 60 A output. |
Use Scenario: Main switching FET in 24 V input, 5 V/30 A isolated forward converter for factory automation PLCs. IC Role / Device Role / Timing Role: Primary-side power switch with unclamped inductive turn-off during fault conditions. Use Value: 320 mJ avalanche rating eliminates need for external clamping circuits, reducing BOM count and board space. |
| Telecom PSU Half-Bridge | Consumer Laptop Adapter |
|
Use Scenario: Low-side switch in LLC resonant half-bridge for 3 kW telecom rectifier modules. IC Role / Device Role / Timing Role: Fast-turning, low-QGD FET synchronized to zero-voltage switching transitions. Use Value: 35 nC QGD and 80 ns trr support clean commutation with minimal shoot-through risk and reduced EMI. |
Use Scenario: Secondary-side synchronous rectifier in 19 V/4.74 A laptop AC-DC adapter. IC Role / Device Role / Timing Role: Source-drain diode used for freewheeling during dead time; VSD = 0.8–1.1 V minimizes forward drop. Use Value: Low VSD and 115 nC Qr reduce reverse recovery loss, improving light-load efficiency by 1.2% over Schottky alternatives. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar N-channel power MOSFET applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| STP110N10F7 | RDS(on) = 9.5 mΩ @ 10 V but higher QG = 120 nC; TO-220FP package with insulated tab. | Lacks mounting-base thermal path; requires insulating pad and separate heatsink interface. | Prefer when isolation from heatsink is mandatory; avoid if board-level thermal management via copper pour is preferred. |
| IRF3205PBF | RDS(on) = 8.0 mΩ @ 10 V but no specified avalanche rating; TO-220 package with higher Rth(j-a) = 62 K/W. | Not qualified for repetitive avalanche stress; unsuitable for unclamped inductive loads. | Select only for cost-sensitive, non-avalanche applications with conservative SOA derating and forced-air cooling. |
Compared with STP110N10F7 and IRF3205PBF, PSMN015-100B offers superior thermal integration via its D2PAK mounting base, verified avalanche ruggedness, and optimized QG/RDS(on) trade-off-making it the preferred choice for compact, high-reliability, high-current power stages where PCB copper acts as primary heatsink.
Availability
PSMN015-100B is available at Aetrix Electronics and suitable for server VRMs, industrial DC-DC converters, and telecom power supplies requiring stable component supply, long-lifecycle support, and traceable sourcing.
Supply support for PSMN015-100B includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on high-volume, high-reliability discrete, logic, and MOSFET solutions, with leadership in automotive-qualified and industrial-grade power components.
This device belongs to the SiliconMAX standard-level TrenchMOS family, engineered specifically for high-efficiency, high-current switching in computing, communications, and industrial power conversion systems.
FAQ
What is the maximum continuous drain current for PSMN015-100B at 100 °C mounting base temperature?
The maximum continuous drain current is 60.8 A at Tmb = 100 °C, as specified in Table 4 (Limiting Values) under VGS = 10 V condition. This reflects thermal derating due to reduced heat transfer efficiency at elevated mounting base temperatures, and must be applied in thermal design calculations alongside Rth(j-mb) = 0.5 K/W.
Is the mounting base electrically isolated from the drain terminal?
No-the mounting base is electrically connected to the drain (Pin 2), as confirmed in Table 2 (Pinning Information) and Figure 14 (Package Outline). This direct connection provides the primary thermal and current path, and requires careful PCB layout to ensure proper grounding or high-voltage isolation depending on circuit topology.
Does PSMN015-100B support gate drive voltages below 10 V?
Yes-VGS(th) ranges from 1 V to 4.4 V across temperature, enabling partial enhancement at 5 V. However, RDS(on) rises significantly below 10 V (e.g., ~32.4 mΩ at 175 °C and 10 V); full-rated performance requires ≥10 V gate drive to maintain low conduction loss and thermal stability.
Can PSMN015-100B be used in synchronous rectification configurations?
Yes-the integrated source-drain diode has VSD = 0.8–1.1 V at 25 A and trr = 80 ns, making it suitable for low-frequency synchronous rectification. For high-frequency (>300 kHz) operation, external MOSFET control is recommended to avoid body-diode conduction and associated reverse recovery losses.
PSMN015-100B,118 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- TrenchMOS™
- Package/Case:
- TO-263-3, D2PAK (2 Leads + Tab), TO-263AB
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- FET Type:
- N-Channel
- Technology:
- MOSFET (Metal Oxide)
- Drain to Source Voltage (Vdss):
- 100 V
- Current - Continuous Drain (Id) @ 25°C:
- 75A (Tc)
- Drive Voltage (Max Rds On, Min Rds On):
- 10V
- Rds On (Max) @ Id, Vgs:
- 15mOhm @ 25A, 10V
- Vgs(th) (Max) @ Id:
- 4V @ 1mA
- Gate Charge (Qg) (Max) @ Vgs:
- 90 nC @ 10 V
- Vgs (Max):
- ±20V
- Input Capacitance (Ciss) (Max) @ Vds:
- 4900 pF @ 25 V
- FET Feature:
- -
- Power Dissipation (Max):
- 300W (Tc)
- Operating Temperature:
- -55°C ~ 175°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- D2PAK
PSMN015-100B,118 FAQ
1.How can I place an order for PSMN015-100B,118 through Aetrix?
Please submit a Request for Quotation (RFQ) for PSMN015-100B,118 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PSMN015-100B,118 reliable?
The price and inventory of PSMN015-100B,118 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PSMN015-100B,118 is usually 5 days.
3.What payment methods are accepted for PSMN015-100B,118?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PSMN015-100B,118 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PSMN015-100B,118?
PSMN015-100B,118 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PSMN015-100B,118 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PSMN015-100B,118?
For technical support, including PSMN015-100B,118 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PSMN015-100B,118 requirements.
6.How does Aetrix verify that PSMN015-100B,118 is sourced from the original manufacturer or authorized distributors?
All PSMN015-100B,118 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PSMN015-100B,118 meets industry standards.
7.What is the process for return or replacement of PSMN015-100B,118?
All PSMN015-100B,118 units undergo pre-shipment inspection (PSI). If there is an issue with PSMN015-100B,118, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PSMN015-100B,118 part is unused and in its original packaging.
Return procedure for PSMN015-100B,118:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
PSMN015-100B,118 Tags

-
BSZ180P03NS3EGATMA1
Infineon Technologies

-
SIRA14DP-T1-GE3
Vishay Siliconix

-
AO4419
Alpha & Omega Semiconductor Inc.

-
SISA14BDN-T1-GE3
Vishay Siliconix

-
PSMN9R5-30YLC,115
Nexperia USA Inc.

-
BUK9Y21-40E,115
Nexperia USA Inc.

-
RTQ035N03HZGTR
Rohm Semiconductor

-
FDMS7680
onsemi

-
RQ3E180BNTB
Rohm Semiconductor

-
STL6N2VH5
STMicroelectronics

-
DMPH4029LFGQ-7
Diodes Incorporated

-
DMT6015LSS-13
Diodes Incorporated
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

