Nexperia USA Inc. PSMN025-100D,118

Overview

PSMN025-100D,118 from Nexperia is a standard-level N-channel TrenchMOS FET in DPAK (SOT428) package, rated for 100 V V_DS, 47 A continuous drain current at T_mb = 25 °C, and 22 mΩ typical R_DS(on) at V_GS = 10 V and T_j = 25 °C. It delivers high power density in DC-to-DC converters and switched-mode power supplies via low thermal resistance (1 K/W R_th(j-mb)) and fast switching (Q_GD = 25 nC).

For engineers reviewing the PSMN025-100D,118 datasheet, PSMN025-100D,118 pinout, PSMN025-100D,118 application, or PSMN025-100D,118 equivalent, key selection criteria include its 100 V blocking capability, 22 mΩ on-resistance at 25 °C, 150 W total power dissipation, avalanche ruggedness (260 mJ), and DPAK thermal mounting base configuration.

Technical Context

This FET employs TrenchMOS silicon technology to achieve low R_DS(on) and high current density while maintaining robust avalanche performance. Its gate threshold voltage (V_GS(th)) ranges from 2–4 V at 25 °C, enabling reliable enhancement-mode operation with standard 10 V gate drive.

The device features integrated source-drain diode with 0.87–1.2 V forward voltage at 25 A and 82 ns reverse recovery time, supporting synchronous rectification. Thermal design centers on junction-to-mounting-base conduction (R_th(j-mb) = 1 K/W), not ambient, making it suitable for PCB-mounted heatsink interfaces.

Key Specifications

Pinout & Package

PSMN025-100D,118 uses the SOT428 (DPAK) plastic surface-mount package with 3 leads and an exposed mounting base electrically connected to the drain terminal. The package supports high-power thermal management via direct metal interface to heatsinks or copper pour.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar N-channel MOSFET applications.

Compared with IRF540NPBF, PSMN025-100D,118 offers 45 % lower R_DS(on) and superior thermal interface; versus STP110N10F7, it trades 11 mΩ for 30 % lower Q_GD and smaller DPAK footprint-favoring high-frequency, space-constrained SMPS.

Availability

PSMN025-100D,118 is available at Aetrix Electronics and suitable for server VRMs, industrial AC-DC front-ends, and telecom DC-DC bricks requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for PSMN025-100D,118 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on high-volume, high-reliability discrete and logic devices, with leadership in automotive-qualified and industrial-grade MOSFETs.

The SiliconMAX standard-level MOSFET product line targets computing, communications, consumer, and industrial power conversion-emphasizing low R_DS(on), robust avalanche capability, and thermally optimized packages like DPAK.

FAQ

What is the maximum continuous drain current for PSMN025-100D,118 at 100 °C mounting base temperature?

At T_mb = 100 °C, the continuous drain current is derated to approximately 33 A per Figure 1 in the datasheet. This value is confirmed in Table 4 (Limiting Values) under "ID drain current" with condition "V_GS = 10 V; T_mb = 100 °C", and reflects thermal equilibrium at the mounting base interface-not ambient or case temperature.

Is PSMN025-100D,118 suitable for linear-mode operation in adjustable LDOs or electronic loads?

Yes-its 150 W total power dissipation and 1 K/W R_th(j-mb) support sustained linear operation up to ~20 A at 30 V drop with appropriate heatsinking. However, SOA curves in Figure 4 confirm safe operation only up to 100 µs pulses at high V_DS; continuous use requires strict thermal monitoring and mounting base temperature control below 100 °C.

Does the mounting base (pin 2) require electrical isolation from the PCB ground plane?

Yes-the mounting base is internally connected to the drain (pin 2), so it must be electrically isolated from any other net, including ground, unless the drain node is intentionally tied to chassis or heatsink potential. Standard practice uses insulating thermal pads or ceramic washers when mounting to grounded heatsinks.

What is the gate threshold voltage range across temperature, and how does it affect drive circuit design?

V_GS(th) ranges from 1 V (min at T_j = 175 °C) to 6 V (max at T_j = −55 °C), with 2–4 V typical at 25 °C. This wide variation means gate drivers must supply ≥10 V to ensure full enhancement across temperature extremes and avoid linear-region operation that increases power loss and thermal stress.