Nexperia USA Inc. PSMN028-100HSX

Overview

PSMN028-100HSX from Nexperia is a dual N-channel standard-level MOSFET in LFPAK56D (SOT1205) package, rated for 100 V drain-source voltage, 27.5 mΩ R_DS(on) at V_GS = 10 V and T_j = 25 °C, and capable of 29 A continuous drain current at T_mb = 25 °C. It integrates two independent FETs optimized for synchronous rectification and high-efficiency DC-DC conversion in industrial power supplies.

For engineers reviewing the PSMN028-100HSX datasheet, PSMN028-100HSX pinout, PSMN028-100HSX application, or PSMN028-100HSX equivalent, key selection criteria include dual-FET integration in a single LFPAK56D footprint, low Q_r (52.8 nC) for reduced switching loss in hard-commutated topologies, and 175 °C maximum junction temperature for high-reliability thermal operation.

Technical Context

This dual MOSFET implements TrenchMOS technology with copper clip construction and flexible leads to minimize parasitic inductance and enhance thermal transfer. Each channel features identical static and dynamic characteristics: matched R_DS(on), Q_G, Q_GD, and C_iss, enabling symmetrical gate drive and balanced current sharing in paralleled or complementary configurations.

The device supports standard-level gate drive (V_GS(th) = 2.4–4 V), operates up to 175 °C junction temperature, and delivers 67 mJ non-repetitive avalanche energy under unclamped inductive switching-critical for robustness in flyback and forward converter primary-side snubbing and secondary-side synchronous rectification.

Key Specifications

Pinout & Package

LFPAK56D (SOT1205) is a dual-power SO8 variant with exposed copper mounting base, 8-lead surface-mount plastic package measuring 4.95 × 5.30 mm with 1.27 mm lead pitch. Its copper clip construction ensures low source inductance and high power density.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual N-channel MOSFET applications.

Compared with IPP036N10N5 and SiHFA200-60, PSMN028-100HSX uniquely combines 100 V rating, dual-FET integration in LFPAK56D, and 52.8 nC Q_r - making it the only option that simultaneously satisfies high-voltage capability, space-constrained synchronous rectification, and low-recovery-loss requirements in industrial SMPS.

Availability

PSMN028-100HSX is available at Aetrix Electronics and suitable for industrial drive inverters, uninterruptible power supplies (UPS), forward/flyback converters, and synchronous rectifier modules requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for PSMN028-100HSX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on high-volume, high-reliability logic, discrete, and MOSFET solutions, with manufacturing rooted in process innovation and automotive-grade quality systems.

PSMN028-100HSX belongs to Nexperia's TrenchMOS dual-FET product line, engineered specifically for space-constrained, high-efficiency power conversion in industrial and telecom infrastructure where thermal robustness and low Q_r are critical.

FAQ

What is the maximum continuous drain current per FET at 100 °C mounting base temperature?

At T_mb = 100 °C, the continuous drain current per FET is 20.4 A, as specified in Table 5 (Limiting values). This value is derived from thermal derating curves in Figure 2 and accounts for junction-to-mounting-base thermal resistance of 2.36 K/W under standard PCB layout conditions.

Can PSMN028-100HSX be used in avalanche-mode operation?

Yes - it is rated for non-repetitive drain-source avalanche energy of 67 mJ under defined conditions (ID = 29 A, V_sup ≤ 100 V, R_GS = 50 Ω, V_GS = 10 V, T_j(init) = 25 °C). This rating is validated per IEC 60134 and limited by 175 °C maximum junction temperature, not package failure.

How does the LFPAK56D package improve thermal performance over standard SO8?

The LFPAK56D uses a copper clip to directly connect the die source to the exposed mounting base, reducing R_th(j-mb) to 2.36 K/W - 42% lower than typical SO8 (≈4.0 K/W). This enables 29 A continuous current at T_mb = 25 °C, whereas standard SO8 would require derating to ~18 A under identical conditions.

Is gate drive isolation required between FET1 and FET2?

No - the gates (G1 and G2) are electrically isolated, but they may be driven in parallel if identical timing and voltage levels are needed. Independent drive is recommended when asymmetric duty cycles or dead-time control is required, such as in active-clamp forward topologies where FET1 and FET2 serve different functional roles.