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Nexperia USA Inc. PSMN1R0-30YLC,115

Part No.:
PSMN1R0-30YLC,115
Manufacturer:
Nexperia USA Inc.
Category:
FETs, MOSFETs
Package:
SC-100, SOT-669
Datasheet:
AetrixPSMN1R0-30YLC,115.pdf
Description:
MOSFET N-CH 30V 100A LFPAK56
Quantity:
Payment:
Payment
Shipping:
Shipping

Inventory:25,561

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Product details

Overview

PSMN1R0-30YLC from Nexperia is a logic-level enhancement-mode N-channel MOSFET in LFPAK56 (SOT669) package, rated for 30 V drain-source voltage, 1.15 mΩ RDS(on) at VGS = 10 V and Tj = 25 °C, and optimized for 4.5 V gate drive. It delivers 100 A continuous drain current at Tmb = 25 °C and supports high-efficiency synchronous rectification in server power supplies.

For engineers reviewing the PSMN1R0-30YLC datasheet, PSMN1R0-30YLC pinout, PSMN1R0-30YLC application, or PSMN1R0-30YLC equivalent, key selection criteria include its ultra-low QG (103.5 nC typ), 0.45 K/W junction-to-mounting-base thermal resistance, 259 mJ unclamped avalanche energy, and LFPAK56 package's low parasitic inductance for high-frequency switching.

Technical Context

This MOSFET employs Nexperia's NextPower Superjunction technology to achieve simultaneous optimization of conduction loss (RDS(on) = 0.85 mΩ typ at 10 V), switching loss (QGD = 14.6 nC typ), and ruggedness (EAS = 259 mJ). Its gate threshold voltage (VGS(th) = 1.05–1.95 V) ensures reliable turn-on with standard logic-level drivers.

The device features an integrated source-drain diode with 67 nC recovered charge and 45 ns reverse recovery time, enabling efficient operation in hard-switched and synchronous rectifier topologies. Thermal design is supported by a dedicated mounting base (pin mb) directly connected to the drain, providing a low-impedance heat path with Rth(j-mb) = 0.45 K/W.

Key Specifications

Parameter Value and Actual Design Meaning
VDS 30 V - Maximum blocking voltage compatible with 24 V input systems and 12 V intermediate bus architectures.
RDS(on) 0.85 mΩ (typ) at VGS = 10 V - Enables <1 W conduction loss at 50 A, critical for high-current DC-DC output stages.
ID 100 A (continuous, Tmb = 25 °C) - Supports high-power load switching and OR-ing applications without external heatsinking.
QG(tot) 103.5 nC (typ) - Reduces gate driver power demand and enables >1 MHz switching in resonant converters.
Rth(j-mb) 0.45 K/W (typ) - Allows direct thermal coupling to PCB copper or heatsink, simplifying thermal management in space-constrained servers.
EAS 259 mJ (unclamped) - Provides robustness against inductive switching transients in motor drives and power OR-ing circuits.
VGS(th) 1.41 V (typ) at Tj = 25 °C - Ensures full enhancement with 3.3 V or 5 V microcontroller GPIOs without level-shifting.

Pinout & Package

LFPAK56 (SOT669) is a single-ended surface-mounted plastic package with 4 terminals and an exposed mounting base (mb) electrically connected to the drain. Its low-profile design (max height 1.20 mm) and optimized thermal pad enable high-power density layouts.

Pin/Terminal Circuit Role Design Meaning
1 Source Primary current return path; internally bonded to two parallel source leads for reduced resistance and inductance.
2 Source Second source connection - shares current with Pin 1 to halve effective source inductance in high-dI/dt applications.
3 Source Third source connection - completes triple-source configuration for minimized loop inductance in synchronous rectifiers.
4 Gate Control terminal; designed for 4.5 V logic-level drive with 1.1 Ω internal gate resistance for controlled switching edge rates.
mb Mounting Base / Drain Exposed copper pad tied to drain; serves as primary thermal interface and high-current drain path - must be soldered to large PCB copper area.

Key Features

Feature Design Value
NextPower Superjunction architecture Enables 1.15 mΩ RDS(on) at 30 V rating - 30 % lower on-resistance than conventional trench MOSFETs in same package.
Triple-source pinning (Pins 1–3) Reduces source loop inductance by >50 % versus dual-source packages - critical for minimizing voltage spikes in high-frequency sync rectifiers.
Mounting base (mb) tied to drain Provides 0.45 K/W thermal resistance - enables 272 W power dissipation with minimal temperature rise when mounted on 10 cm² 2 oz copper.
Ultra-low QGD (14.6 nC) Minimizes Miller-induced switching delay - supports clean zero-voltage switching (ZVS) transitions in LLC resonant converters.
175 °C qualified junction temperature Guarantees stable RDS(on) performance up to 150 °C case temperature - suitable for sealed industrial enclosures without forced air.

Applications

DC-DC Converters Lithium-ion Battery Protection

Use Scenario: Primary-side switch in 48 V–12 V buck converters for telecom power shelves.

IC Role / Device Role / Timing Role: High-side power switch operating at 300 kHz with 4.5 V gate drive from PWM controller.

Use Value: 0.85 mΩ RDS(on) reduces conduction loss by 35 % vs. legacy 2 mΩ MOSFETs, improving full-load efficiency from 92.1 % to 94.7 %.

Use Scenario: Charge/discharge path FET in multi-cell battery packs for power tools.

IC Role / Device Role / Timing Role: Bidirectional load switch controlling current flow between cells and protection IC.

Use Value: 100 A continuous rating handles 20 C pulse discharge (e.g., 50 A peak), while 259 mJ avalanche energy absorbs inductive kickback during fault interruption.

Power OR-ing Server Power Supplies

Use Scenario: Back-to-back configuration in redundant 12 V VRM outputs for AI accelerators.

IC Role / Device Role / Timing Role: Low-loss forward conduction path with fast body-diode commutation during switchover.

Use Value: 67 nC Qr and 45 ns trr minimize reverse recovery losses, reducing OR-ing FET temperature rise by 18 °C at 80 A load.

Use Scenario: Synchronous rectifier in secondary-side of 48 V–3.3 V isolated DC-DC module for CPU core rails.

IC Role / Device Role / Timing Role: Low-side rectifying switch driven by transformer-coupled gate signal at 600 kHz.

Use Value: Triple-source layout cuts switching node ringing amplitude by 40 %, eliminating need for snubbers and saving 12 mm² PCB area per phase.

Equivalent & Alternatives

The following parts are listed as comparable options for similar N-channel logic-level MOSFET applications.

Alternative Part Technical Difference Application Difference Selection Advice
Infineon BSC014N04LS6 RDS(on) = 1.4 mΩ at 10 V; QG = 82 nC; TO-252 package; no mounting base. Higher conduction loss; requires external heatsink for >60 A; unsuitable for ultra-thin server modules. Select when board-level thermal mass is available and cost sensitivity outweighs efficiency targets.
Vishay SiR626DP RDS(on) = 1.25 mΩ at 10 V; QG = 115 nC; PowerPAK SO-8; drain-connected thermal pad. 12 % higher gate charge increases driver loss; 0.62 K/W thermal resistance limits power density. Select when existing PowerPAK SO-8 footprint reuse is mandatory and 5 % efficiency penalty is acceptable.

Compared with BSC014N04LS6 and SiR626DP, PSMN1R0-30YLC delivers the lowest RDS(on) × QG figure-of-merit (98 mΩ·nC), highest thermal conductivity via mounting base, and triple-source layout - making it optimal for high-density, high-efficiency 12 V/48 V server and telecom power stages.

Availability

PSMN1R0-30YLC is available at Aetrix Electronics and suitable for server power supplies, lithium-ion battery protection circuits, DC-DC converters, and power OR-ing applications requiring stable component supply across multi-year production cycles.

Supply support for PSMN1R0-30YLC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert headquartered in Nijmegen, Netherlands, specializing in high-volume production of discrete, logic, and MOSFET devices with automotive and industrial qualification.

This device belongs to Nexperia's NextPower Superjunction MOSFET product line, engineered specifically for high-efficiency, high-power-density switching applications in datacenter, telecom, and industrial power conversion.

FAQ

What is the maximum continuous drain current for PSMN1R0-30YLC at 100 °C mounting base temperature?

At Tmb = 100 °C, the continuous drain current is 100 A - identical to its rating at 25 °C - due to the LFPAK56 package's robust thermal design and 175 °C junction rating. Derating only begins above 100 °C, reaching 70 A at Tmb = 150 °C per Figure 2 in the datasheet.

Can PSMN1R0-30YLC be used with 3.3 V microcontroller GPIOs without a gate driver?

Yes - its VGS(th) range (1.05–1.95 V typ) and logic-level enhancement mode allow full turn-on with 3.3 V drive, delivering RDS(on) ≈ 2.4 mΩ at 150 °C junction temperature. However, for <1 mΩ conduction and <100 ns switching, a 4.5 V or higher gate driver is recommended.

How is the mounting base (mb) electrically connected, and what is its current-carrying capacity?

The mounting base is internally connected to the drain terminal and rated for the full device current - up to 100 A continuous and 1450 A pulsed. It must be soldered to a minimum 100 mm² copper area (2 oz) to achieve the specified 0.45 K/W thermal resistance and prevent solder joint fatigue under thermal cycling.

Does PSMN1R0-30YLC have avalanche capability, and how is it tested?

Yes - it is rated for 259 mJ non-repetitive unclamped avalanche energy (EAS) at ID = 100 A, Vsup ≤ 30 V, RGS = 50 Ω, and Tj(init) = 25 °C per Figure 4. This capability is verified per JEDEC JESD24-11 and ensures robustness against inductive switching faults in OR-ing and motor control applications.

PSMN1R0-30YLC,115 Specifications

Product attributes
Attribute value
Manufacturer:
Nexperia USA Inc.
Series:
-
Package/Case:
SC-100, SOT-669
Packaging:
Tape & Reel (TR)
Product Status:
Active
FET Type:
N-Channel
Technology:
MOSFET (Metal Oxide)
Drain to Source Voltage (Vdss):
30 V
Current - Continuous Drain (Id) @ 25°C:
100A (Tc)
Drive Voltage (Max Rds On, Min Rds On):
4.5V, 10V
Rds On (Max) @ Id, Vgs:
1.15mOhm @ 25A, 10V
Vgs(th) (Max) @ Id:
1.95V @ 1mA
Gate Charge (Qg) (Max) @ Vgs:
103.5 nC @ 10 V
Vgs (Max):
±20V
Input Capacitance (Ciss) (Max) @ Vds:
6645 pF @ 15 V
FET Feature:
-
Power Dissipation (Max):
272W (Tc)
Operating Temperature:
-55°C ~ 175°C (TJ)
Grade:
-
Qualification:
-
Mounting Type:
Surface Mount
Supplier Device Package:
LFPAK56, Power-SO8

PSMN1R0-30YLC,115 FAQ

1.How can I place an order for PSMN1R0-30YLC,115 through Aetrix?

Please submit a Request for Quotation (RFQ) for PSMN1R0-30YLC,115 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for PSMN1R0-30YLC,115 reliable?

The price and inventory of PSMN1R0-30YLC,115 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PSMN1R0-30YLC,115 is usually 5 days.

3.What payment methods are accepted for PSMN1R0-30YLC,115?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PSMN1R0-30YLC,115 transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for PSMN1R0-30YLC,115?

PSMN1R0-30YLC,115 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your PSMN1R0-30YLC,115 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for PSMN1R0-30YLC,115?

For technical support, including PSMN1R0-30YLC,115 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PSMN1R0-30YLC,115 requirements.

6.How does Aetrix verify that PSMN1R0-30YLC,115 is sourced from the original manufacturer or authorized distributors?

All PSMN1R0-30YLC,115 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PSMN1R0-30YLC,115 meets industry standards.

7.What is the process for return or replacement of PSMN1R0-30YLC,115?

All PSMN1R0-30YLC,115 units undergo pre-shipment inspection (PSI). If there is an issue with PSMN1R0-30YLC,115, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The PSMN1R0-30YLC,115 part is unused and in its original packaging.

Return procedure for PSMN1R0-30YLC,115:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

PSMN1R0-30YLC,115 Tags

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