Nexperia USA Inc. PSMN1R0-30YLD/2X

Overview

PSMN1R0-30YLD from Nexperia is an N-channel logic-level power MOSFET in LFPAK56 (SOT669) package, rated for 30 V V_DS, 1.0 mΩ R_DS(on) @ 4.5 V V_GS, and 300 A continuous drain current at T_mb = 25 °C. It employs NextPowerS3 technology with "SchottkyPlus" body diode for soft-recovery (s-factor > 0.95), ultra-low Q_G (38.2 nC typ @ 4.5 V), and avalanche-rated ruggedness (190 A I_AS). It is engineered for high-efficiency, high-frequency synchronous rectification in server DC-DC converters.

For engineers reviewing the PSMN1R0-30YLD datasheet, PSMN1R0-30YLD pinout, PSMN1R0-30YLD application, or PSMN1R0-30YLD equivalent, key selection criteria include its 4.5 V logic-level gate drive compatibility, 0.56 K/W junction-to-mounting-base thermal resistance, Schottky-like diode performance with <1 µA leakage at 25 °C, and LFPAK56 clip-bonded construction qualified to 175 °C.

Technical Context

This MOSFET uses Nexperia's NextPowerS3 architecture with integrated "SchottkyPlus" body diode-delivering soft reverse recovery (t_rr = 51.8–103.6 ns, Q_r = 67.1–134.2 nC) and low EMI without elevated leakage. Its gate charge profile (Q_GD = 10.9–16.35 nC, Q_G(tot) = 38.2–57.3 nC @ 4.5 V) enables fast switching (t_d(on) = 32.4 ns, t_f = 31.7 ns) with minimal spiking under high dV/dt conditions.

The device features a 4-terminal LFPAK56 package with three parallel source pins, one gate pin, and a drain-connected mounting base. Its thermal design leverages low parasitic inductance/resistance and solderable exposed leads, achieving R_th(j-mb) = 0.56 K/W and supporting 238 W total power dissipation at T_mb = 25 °C.

Key Specifications

Pinout & Package

PSMN1R0-30YLD is housed in the LFPAK56 (SOT669) package-a clip-bonded, wave-solderable Power-SO8 variant with no wire bonds or die attach glue. The mounting base is electrically connected to the drain and serves as the primary thermal path.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar N-channel logic-level power MOSFET applications.

Compared with IRF7759L2TRPBF and SiR626DP, PSMN1R0-30YLD uniquely combines true 4.5 V logic-level operation, industry-leading 0.56 K/W thermal resistance, and SchottkyPlus soft-recovery-making it optimal for space-constrained, high-frequency, high-current synchronous rectification where gate drive simplicity and thermal headroom are critical.

Availability

PSMN1R0-30YLD is available at Aetrix Electronics and suitable for server DC-DC conversion, telecom secondary-side rectification, and VRM/point-of-load modules requiring stable component supply, high-current capability, and 175 °C reliability.

Supply support for PSMN1R0-30YLD includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on essential semiconductors - high-volume, high-reliability components for automotive, industrial, computing, and consumer applications.

PSMN1R0-30YLD belongs to the NextPowerS3 portfolio, designed specifically for high-efficiency, high-frequency power conversion where low conduction loss, soft switching, and thermal robustness are required in compact form factors.

FAQ

What is the maximum continuous drain current for PSMN1R0-30YLD at 100 °C mounting base temperature?

At T_mb = 100 °C, the continuous drain current is derated to 255 A per the datasheet Fig. 2. This reflects thermal limitation of the package and PCB layout-not intrinsic device failure. Practical current is governed by thermal design, including copper area, layer count, and airflow.

Does PSMN1R0-30YLD require a gate resistor for stability in high-frequency switching?

Yes - a small external gate resistor (typically 1–5 Ω) is recommended to dampen ringing caused by PCB trace inductance interacting with low gate input capacitance (C_iss = 5732 pF). The device's low Q_GD and fast switching make it sensitive to layout-induced oscillation without proper gate control.

Can PSMN1R0-30YLD be used in linear-mode (saturation) applications such as electronic loads?

No - it is optimized for switching operation only. Its Safe Operating Area (SOA) limits pulsed current to 1441 A for 10 µs at V_DS = 10 V (Fig. 3), but linear-mode operation risks thermal runaway due to positive temperature coefficient of R_DS(on) and lack of SOA characterization beyond pulse conditions.

Is the mounting base electrically isolated from the source or gate terminals?

No - the mounting base is internally connected to the drain terminal, as confirmed in Pinning Table 2 and Package Outline Fig. 17. It must be routed to the drain net on the PCB and thermally coupled to a heatsink or ground plane designated for drain potential.