Nexperia USA Inc. PSMN1R0-30YLEX
- Part No.:
- PSMN1R0-30YLEX
- Manufacturer:
- Nexperia USA Inc.
- Category:
- FETs, MOSFETs
- Package:
- SC-100, SOT-669
- Datasheet:
-
PSMN1R0-30YLEX.pdf
- Description:
- PSMN1R0-30YLE/SOT669/LFPAK
- Quantity:
- Payment:

- Shipping:

Inventory:4,500
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Product details
Overview
PSMN1R0-30YLE from Nexperia is an N-channel 30 V ASFET in LFPAK56 (SOT669) package, optimized for hot-swap, inrush current limiting, and linear-mode operation with enhanced Safe Operating Area (SOA). It delivers 1.1 mΩ RDS(on) at VGS = 10 V / Tj = 25 °C, supports 275 A continuous drain current (Tmb = 25 °C), and features copper-clip construction for low parasitic inductance - deployed in 12–20 V e-Fuse and DC load-switch applications.
For engineers reviewing the PSMN1R0-30YLE datasheet, PSMN1R0-30YLE pinout, PSMN1R0-30YLE application, or PSMN1R0-30YLE equivalent, key selection criteria include SOA robustness in linear mode, thermal resistance to mounting base (Rth(j-mb) = 0.37 K/W typ), gate charge profile (QG(tot) = 33 nC typ at 4.5 V), and LFPAK56 footprint compatibility with high-current PCB layouts.
Technical Context
This ASFET employs a trench-gate MOSFET structure with copper-clip interconnects to minimize RDS(on) and package inductance. Its SOA curve is specifically extended for linear-mode operation up to 1303 A peak (tp ≤ 10 µs) and sustained 275 A continuous current under optimized thermal mounting.
The device integrates a robust source-drain diode with soft reverse recovery (S = 0.95) and low VSD (0.78 V typ at IS = 25 A), enabling bidirectional current handling in battery protection and hot-swap circuits without external freewheeling diodes.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VDS | 30 V maximum - defines absolute upper rail voltage for safe operation in 12–20 V systems with margin against transients. |
| RDS(on) | 0.94–1.11 mΩ at VGS = 10 V / Tj = 25 °C - enables sub-1 mΩ conduction loss in high-current load switches and e-Fuses. |
| ID cont. | 275 A at Tmb = 25 °C - validated continuous current capability under ideal thermal mounting, limited by PCB copper area and heatsinking. |
| QG(tot) | 33 nC typ at VGS = 4.5 V - determines gate drive energy and switching speed in fast-turn-on hot-swap controllers. |
| Rth(j-mb) | 0.37 K/W typ - enables efficient heat transfer from die to PCB mounting base, critical for linear-mode thermal stability. |
| VGS(th) | 1.2–2.2 V - ensures reliable turn-on with standard 3.3 V or 5 V logic-level gate drivers. |
| EAS | 1.5 J non-repetitive avalanche energy - provides single-pulse ruggedness during inductive load interruption or fault events. |
Pinout & Package
LFPAK56 (SOT669) is a 4-terminal, single-ended surface-mount plastic package with exposed copper mounting base (drain-connected), optimized for high-current, low-inductance, and high-reliability power switching. Its 30 mm² footprint supports >200 A thermal current capacity when mounted on ≥25.4 mm² 70 µm copper.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 2, 3 | Source (S) | Three parallel source terminals reduce bond-wire inductance and improve current sharing in high-di/dt linear-mode operation. |
| 4 | Gate (G) | Single gate input with low RG (3.1 Ω typ) - minimizes Miller-induced oscillation risk during fast switching. |
| Mounting Base (mb) | Drain (D) | Exposed copper pad electrically connected to drain - serves as primary thermal path and high-current return path; requires soldered PCB connection. |
Key Features
| Feature | Design Value |
|---|---|
| Enhanced SOA for linear mode | Extended safe operating area validated up to 1303 A peak and 275 A continuous - enables stable operation in active current limiting without thermal runaway. |
| Low RDS(on) + copper clip | 0.94 mΩ typ RDS(on) with <1 nH package inductance - reduces I²R losses and voltage overshoot during hot-swap insertion. |
| High-reliability LFPAK56 | Qualified to 175 °C junction temperature and 260 °C peak soldering - supports industrial and telecom equipment with extended lifetime requirements. |
| Soft-recovery source-drain diode | S = 0.95 softness factor and 34 ns trr - suppresses voltage spikes and EMI during reverse recovery in bidirectional load switching. |
| Low leakage & threshold stability | IDSS < 1 µA at 25 °C; ΔVGS(th)/ΔT = −3.7 mV/K - ensures predictable turn-on behavior across −55 °C to 150 °C ambient range. |
Applications
| Hot Swap Power Insertion | e-Fuse Protection |
|---|---|
|
Use Scenario: Controlled insertion of line cards into live backplanes operating at 12–20 V. IC Role / Device Role / Timing Role: Main power switch regulating inrush current via linear-mode gate bias control during ramp-up. Use Value: Prevents bus voltage droop and system reset by limiting peak inrush to <50 A while sustaining 200+ A steady-state load. |
Use Scenario: Overcurrent protection in server VRMs and PoE PDs where fast trip (<100 µs) and auto-retry are required. IC Role / Device Role / Timing Role: High-side current-limiting element controlled by external current-sense amplifier and comparator. Use Value: Enables precise 50–250 A current limiting with <1.5 mΩ sense-path contribution, minimizing power loss and thermal derating. |
| DC Load Switching | Battery Protection |
|
Use Scenario: Remote ON/OFF control of high-current subsystems (e.g., GPU rails, storage arrays) in data center power distribution. IC Role / Device Role / Timing Role: Low-loss, high-reliability main switch with integrated SOA margin for transient overloads. Use Value: Delivers <0.5 W conduction loss at 200 A, eliminating need for parallel FETs and reducing BOM count and layout area. |
Use Scenario: Bidirectional current control in 2-cell Li-ion battery packs (8.4 V max) for charge/discharge path isolation and short-circuit cutoff. IC Role / Device Role / Timing Role: Dual-function switch supporting forward conduction and reverse recovery during cell balancing or fault clearing. Use Value: Leverages low VSD (0.78 V) and soft diode recovery to avoid voltage spikes during pack reversal or fault events. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-current hot-swap MOSFET applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Infineon IPP020N04L | 40 V rating, 2.0 mΩ RDS(on), TO-252 package, higher Rth(j-a) (50 K/W) | Limited to lower-current hot-swap due to larger RDS(on) and inferior SOA in linear mode | Choose only if 40 V headroom is mandatory and thermal design allows higher conduction loss. |
| Vishay SiR626DP | 30 V rating, 1.25 mΩ RDS(on), PowerPAK SO-8, no copper clip, SOA not specified for linear mode | Unverified linear-mode ruggedness; higher package inductance increases switching overshoot | Acceptable for switched-mode load switching but not recommended for sustained linear-mode e-Fuse operation. |
Compared with IPP020N04L and SiR626DP, PSMN1R0-30YLE offers superior linear-mode SOA, lower RDS(on), and lower Rth(j-mb), making it uniquely suited for high-reliability hot-swap and e-Fuse designs requiring stable current limiting without thermal runaway.
Availability
PSMN1R0-30YLE is available at Aetrix Electronics and suitable for hot-swap power insertion, e-Fuse protection, and DC load switching applications requiring stable component supply, high-current reliability, and linear-mode ruggedness.
Supply support for PSMN1R0-30YLE includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on high-volume, high-reliability discrete and logic devices, with leadership in advanced packaging and automotive-qualified components.
This device belongs to Nexperia's ASFET (Advanced Superjunction FET) product line, engineered specifically for high-efficiency, high-ruggedness power switching in linear and switched-mode hot-swap, e-Fuse, and load-switch applications.
FAQ
What is the maximum continuous drain current for PSMN1R0-30YLE under real-world PCB conditions?
The datasheet specifies 275 A at Tmb = 25 °C with ideal mounting - but practical current is constrained by PCB copper area, thermal vias, and ambient temperature. With ≥25.4 mm² 70 µm copper and 20 thermal vias, 150–180 A continuous is achievable at Tmb ≤ 85 °C. Derating curves in Figure 2 must be applied per actual board thermal design.
Can PSMN1R0-30YLE be used in avalanche mode for clamping?
Yes - it is 100% tested for non-repetitive avalanche with EAS = 1.5 J (Vsup ≤ 30 V, ID = 25 A, Tj(init) = 25 °C). However, repetitive avalanche is not rated; use only for single-event fault clamping. Thermal limits and SOA boundaries must be strictly observed during testing.
Does the LFPAK56 package require special soldering profiles?
Yes - the mounting base demands full reflow coverage. The recommended profile uses peak temperature ≤260 °C for ≤30 s, with preheat (150–200 °C), soak (180–200 °C for 60–120 s), and ramp-up (≤3 °C/s) per JEDEC J-STD-020. Incomplete wetting of the mb pad causes thermal failure and premature SOA collapse.
How does the triple-source-pin configuration improve performance?
The three parallel source terminals reduce total source inductance and distribute current more evenly across bond wires, lowering di/dt-induced voltage spikes during fast switching and improving current sharing in linear-mode operation. This directly enhances SOA margin and reduces localized heating at the source interface.
PSMN1R0-30YLEX Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- -
- Package/Case:
- SC-100, SOT-669
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- FET Type:
- N-Channel
- Technology:
- MOSFET (Metal Oxide)
- Drain to Source Voltage (Vdss):
- 30 V
- Current - Continuous Drain (Id) @ 25°C:
- 275A (Tc)
- Drive Voltage (Max Rds On, Min Rds On):
- 7V, 10V
- Rds On (Max) @ Id, Vgs:
- 1.11mOhm @ 25A, 10V
- Vgs(th) (Max) @ Id:
- 2.2V @ 2mA
- Gate Charge (Qg) (Max) @ Vgs:
- 119 nC @ 10 V
- Vgs (Max):
- ±20V
- Input Capacitance (Ciss) (Max) @ Vds:
- 7389 pF @ 15 V
- FET Feature:
- -
- Power Dissipation (Max):
- 224W (Tc)
- Operating Temperature:
- -55°C ~ 175°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- LFPAK56, Power-SO8
PSMN1R0-30YLEX FAQ
1.How can I place an order for PSMN1R0-30YLEX through Aetrix?
Please submit a Request for Quotation (RFQ) for PSMN1R0-30YLEX on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PSMN1R0-30YLEX reliable?
The price and inventory of PSMN1R0-30YLEX are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PSMN1R0-30YLEX is usually 5 days.
3.What payment methods are accepted for PSMN1R0-30YLEX?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PSMN1R0-30YLEX transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PSMN1R0-30YLEX?
PSMN1R0-30YLEX orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PSMN1R0-30YLEX order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PSMN1R0-30YLEX?
For technical support, including PSMN1R0-30YLEX datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PSMN1R0-30YLEX requirements.
6.How does Aetrix verify that PSMN1R0-30YLEX is sourced from the original manufacturer or authorized distributors?
All PSMN1R0-30YLEX products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PSMN1R0-30YLEX meets industry standards.
7.What is the process for return or replacement of PSMN1R0-30YLEX?
All PSMN1R0-30YLEX units undergo pre-shipment inspection (PSI). If there is an issue with PSMN1R0-30YLEX, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PSMN1R0-30YLEX part is unused and in its original packaging.
Return procedure for PSMN1R0-30YLEX:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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