Nexperia USA Inc. PSMN1R0-40YLD/1X

Overview

PSMN1R0-40YLD from Nexperia is an N-channel logic-level power MOSFET in LFPAK56 (SOT1023) package, rated for 40 V V_DS, 1.1 mΩ R_DS(on) @ V_GS = 4.5 V and 25 A, 280 A continuous drain current capability at T_mb = 25 °C, and qualified to 150 °C junction temperature. It employs NextPower-S3 Schottky-Plus technology for soft-recovery synchronous rectification in high-efficiency server PSUs.

For engineers reviewing the PSMN1R0-40YLD datasheet, PSMN1R0-40YLD pinout, PSMN1R0-40YLD application, or PSMN1R0-40YLD equivalent, key selection criteria include its 4.5 V logic-level gate drive compatibility, 17 nC Q_GD, avalanche-rated ruggedness (190 A I_AS), low 0.56 K/W R_th(j-mb), and LFPAK56 copper-clip thermal performance.

Technical Context

This MOSFET uses TrenchMOS Superjunction architecture with Schottky-Plus body diode integration, enabling soft reverse recovery (t_rr = 48 ns, Q_r = 67 nC) without elevated I_DSS leakage. Its gate threshold voltage (V_GS(th) = 1.05–2.2 V) and low Q_G(tot) = 59 nC @ 4.5 V ensure fast, efficient switching in high-frequency DC-DC topologies.

The LFPAK56 package features exposed mounting base connected to drain, three parallel source terminals, and a single gate terminal - optimized for low-inductance, high-current PCB layouts with wave-solderable leads and visual solder-joint inspection. Thermal resistance from junction to mounting base is 0.56 K/W typical.

Key Specifications

Pinout & Package

LFPAK56 (SOT1023) is a copper-clip, surface-mount plastic package with exposed mounting base (drain), three paralleled source terminals, and one gate terminal. It delivers low parasitic inductance/resistance and supports wave soldering with visual joint inspection.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-current logic-level MOSFET applications.

Compared with IPP026N04L and SiR626DP, PSMN1R0-40YLD uniquely combines 1.1 mΩ on-resistance, 17 nC Q_GD, 190 A avalanche rating, and 0.56 K/W thermal resistance in a wave-solderable LFPAK56 - making it optimal for high-density, high-reliability server and telecom power stages.

Availability

PSMN1R0-40YLD is available at Aetrix Electronics and suitable for high-efficiency server power supplies, synchronous rectification modules, and industrial motor control inverters requiring stable component supply across multi-year production cycles.

Supply support for PSMN1R0-40YLD includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on essential semiconductors, with leadership in discrete devices, logic ICs, and MOSFETs for power management and signal integrity.

This device belongs to Nexperia's NextPower-S3 portfolio - engineered specifically for high-current, high-frequency power conversion where low Q_GD, soft recovery, and thermal reliability are critical.

FAQ

What is the maximum continuous drain current for PSMN1R0-40YLD at 100 °C mounting base temperature?

At T_mb = 100 °C, the continuous drain current is derated to 198 A per the datasheet Fig. 2. This reflects thermal limitation of the LFPAK56 package under real-world board-level cooling conditions - not a silicon limit. The 280 A rating applies only at T_mb = 25 °C with ideal heatsinking.

Does PSMN1R0-40YLD require a negative gate turn-off voltage to prevent shoot-through?

No. Its gate threshold voltage (V_GS(th) = 1.05–2.2 V) and low gate leakage (<100 nA) allow safe operation with 0 V turn-off in half-bridge configurations. The 20 V absolute maximum V_GS rating permits use of simple 0 V / +5 V or 0 V / +4.5 V gate drive schemes without negative bias circuitry.

Can PSMN1R0-40YLD be used in linear mode (saturation region) for precision current regulation?

No. It is optimized for switching operation only. The Safe Operating Area (SOA) curve (Fig. 3) shows limited linear-mode capability - maximum DC power dissipation is 198 W at T_mb = 25 °C, but pulse SOA collapses rapidly above 100 µs. Not characterized or qualified for analog linear regulation.

Is the mounting base (drain) electrically isolated from the PCB copper pour in standard layout?

No. The mounting base is the drain terminal and must be connected to the high-side DC bus or drain node. Standard layout uses a large, thermally enhanced copper pour tied directly to the drain pad. Electrical isolation would require dielectric thermal interface material and violates the qualified thermal test setup per datasheet Fig. 5.